EPM9560RI208-20 ApplicationField
-5G Technology
-Consumer Electronics
-Artificial Intelligence
-Internet of Things
-Cloud Computing
-Industrial Control
-Medical Equipment
-Wireless Technology
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EPM9560RI208-20 FAQ Chips
Q: Where can I purchase INTEL EPM9560 Development Boards, Evaluation Boards, or MAX 9000 EPLD Starter Kit? also provide technical information?
A: RAYPCB does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
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Q: How can I obtain software development tools related to the INTEL FPGA platform?
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ICs EPM9560RI208-20 Features
■ Programmable output slew-rate control reduces switching noise
– Dedicated carry chain that implements arithmetic functions such
device (PLD) family (see Table 1)
– Low power consumption (typical specification is 0.5 mA or less in
circuitry compliant with IEEE Std. 1149.1-1990 on selected devices
megafunctions)
■ Flexible interconnect
while I/O pins are compatible with 5.0-V and 3.3-V logic levels
devices or intelligent controller
software tools and megafunctions)
– Built-in Joint Test Action Group (JTAG) boundary-scan test (BST)
Special Interest Group (PCI SIG) PCI Local Bus Specification,
as fast adders, counters, and comparators (automatically used by
– Fully compliant with the peripheral component interconnect
standby mode)
■ System-level features
■ Low-cost, high-density, register-rich CMOS programmable logic
■ Powerful I/O pins
– MultiVoltTM I/O interface enabling device core to run at 5.0 V,
logic functions (automatically used by software tools and
– 282 to 1,500 registers
– 2,500 to 16,000 usable gates
predictable interconnect delays
Revision 2.2 for 5.0-V operation
– FastTrack Interconnect continuous routing structure for fast,
– Tri-state emulation that implements internal tri-state nets
– In-circuit reconfigurability (ICR) via external configuration
– Dedicated cascade chain that implements high-speed, high-fan-in
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Xilinx EPM9560RI208-20 Overview
General
Description
The MAX 9000 family of in-system-programmable, high-density, highperformance EPLDs is based on Altera’s third-generation MAX
architecture. Fabricated on an advanced CMOS technology, the EEPROMbased MAX 9000 family provides 6,000 to 12,000 usable gates, pin-to-pin
delays as fast as 10 ns, and counter speeds of up to 144 MHz. The -10 speed
grade of the MAX 9000 family is compliant with the PCI Local Bus
Specification, Revision 2.2. Table 3 shows the speed grades available for
MAX 9000 devices.
Features
■ High-performance CMOS EEPROM-based programmable logic
devices (PLDs) built on third-generation Multiple Array MatriX (MAX®) architecture
■ 5.0-V in-system programmability (ISP) through built-in IEEE Std.
1149.1 Joint Test Action Group (JTAG) interface
■ Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE
Std. 1149.1-1990
■ High-density erasable programmable logic device (EPLD) family
ranging from 6,000 to 12,000 usable gates (see Table 1)
■ 10-ns pin-to-pin logic delays with counter frequencies of up to
144 MHz
■ Fully compliant with the peripheral component interconnect Special
Interest Group’s (PCI SIG) PCI Local Bus Specification, Revision 2.2
■ Dual-output macrocell for independent use of combinatorial and
registered logic
■ FastTrack® Interconnect for fast, predictable interconnect delays
■ Input/output registers with clear and clock enable on all I/O pins
■ Programmable output slew-rate control to reduce switching noise
■ MultiVolt™ I/O interface operation, allowing devices to interface
with 3.3-V and 5.0-V devices
■ Configurable expander product-term distribution allowing up to 32
product terms per macrocell
■ Programmable power-saving mode for more than 50% power
reduction in each macrocell
■ Programmable macrocell flipflops with individual clear, preset,
clock, and clock enable controls
■ Programmable security bit for protection of proprietary designs
■ Software design support and automatic place-and-route provided by
Altera’s MAX+PLUS® II development system on Windows based
PCs as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM
RISC System/6000 workstations
■ Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Synopsys, Synplicity, and VeriBest
■ Programming support with Altera’s Master Programming Unit
(MPU), BitBlasterTM serial download cable, ByteBlasterT parallel port download cable, and ByteBlasterMVTM parallel port download
cable, as well as programming hardware from third-party manufacturers
■ Offered in a variety of package options with 84 to 356 pins (see
Table 2
The INTEL CPLDs series EPM9560RI208-20 is Complex EEPLD, 208 Pins, 560 Cells, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
EPM9560RI208-20 Tags integrated circuit
1. INTEL MAX 9000 Devices development board
2. MAX 9000 Devices EPM9560
3. MAX 9000 Devices starter kit
4. EPM9560 development board
5. INTEL EPM9560
6. EPM9560RI208-20 Datasheet PDF
7. EPM9560 evaluation board
8. MAX 9000 Devices evaluation kit
9. EPM9560 development board
Xilinx EPM9560RI208-20 TechnicalAttributes
-Number of Macrocells 560
-Package / Case 208-BFQFP Exposed Pad
-Mounting Type Surface Mount
-Delay Time tpd(1) Max 20.0ns
-Supplier Device Package 208-RQFP (28×28)
-Programmable Type In System Programmable
-Number of I/O 153
-Number of Gates 12000
-Operating Temperature -40℃ ~ 85℃ (TA)
-Voltage Supply – Internal 4.5V ~ 5.5V
-Number of Logic Elements/Blocks 35
