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ISPLSI1048E-50LT FAQ Chips
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ICs ISPLSI1048E-50LT Features
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Xilinx ISPLSI1048E-50LT Overview
The ispLSI 1048E is a High Density Programmable Logic Device containing 288 Registers, 96 Universal I/O pins, 12 Dedicated Input pins, four Dedicated Clock Input pins, two dedicated Global OE input pins, and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1048E offers 5V non-volatile in-system programmability of the logic, as well as the interconnect to provide truly reconfigurable systems. A functional superset of the ispLSI 1048 architecture, the ispLSI 1048E device adds two new global output enable pins and two additional dedicated inputs.
The basic unit of logic on the ispLSI 1048E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1…F7 (see ISPLSI1048E-50LT Datasheet). There are a total of 48 GLBs in the ispLSI 1048E device. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device.
ISPLSI1048E-50LT Tags integrated circuit
1. ISPLSI1048E-50LT Datasheet PDF
2. CPLD ispLSI 1000 ISPLSI1048E
3. ISPLSI1048E development board
4. ISPLSI1048E reference design
5. CPLD ispLSI 1000 starter kit
6. Lattice CPLD ispLSI 1000 development board
7. CPLD ispLSI 1000 evaluation kit
8. Lattice ISPLSI1048E
9. ISPLSI1048E reference design
Xilinx ISPLSI1048E-50LT TechnicalAttributes
-Supply Voltage – Min 4.75 V
-Supply Voltage – Max 5.25 V
-Number of Programmable I/Os 96
-Maximum Operating Temperature + 70 C
-Supply Current 175 mA
-Memory Type EEPROM
-Number of Macrocells 192
-Mounting Style SMD/SMT
-Delay Time 20 ns
-Maximum Operating Frequency 50 MHz
-Minimum Operating Temperature 0 C
-Package / Case TQFP-128
-Operating Supply Voltage 4.75 V to 5.25 V