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ISPLSI5256VE-125LT128-100I FAQ Chips
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ICs ISPLSI5256VE-125LT128-100I Features
Second Generation SuperWIDE HIGH DENSITY
IN-SYSTEM PROGRAMMABLE LOGIC DEVICE
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Xilinx ISPLSI5256VE-125LT128-100I Overview
The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting theGLBs.
Outputs from the GLBs drive the Global Routing Pool (GRP) between the GLBs. Switching resources are provided to allow signals in the Global Routing Pool to driveany or all the GLBs in the device. This mechanism allows fast, efficient connections across the entire device.
Each GLB contains 32 macrocells and a fully populated,programmable AND-array with 160 logic product termsand three extra control product terms. The GLB has 68 inputs from the Global Routing Pool which are available in both true and complement form for every product term.
The 160 product terms are grouped in 32 sets of five and sent into a Product Term Sharing Array (PTSA) which allows sharing up to a maximum of 35 product terms for a single function. Alternatively, the PTSA can be bypassed for functions of five product terms or less. The three extra product terms are used for shared controls:reset, clock,
clock enable and output enable.
ISPLSI5256VE-125LT128-100I Tags integrated circuit
1. SuperWIDE High Density PLD starter kit
2. Lattice ispLSI5256VE
3. ispLSI5256VE reference design
4. ispLSI5256VE development board
5. SuperWIDE High Density PLD evaluation kit
6. SuperWIDE High Density PLD ispLSI5256VE
7. Lattice SuperWIDE High Density PLD development board
8. ISPLSI5256VE-125LT128-100I Datasheet PDF
9. ispLSI5256VE development board
Xilinx ISPLSI5256VE-125LT128-100I TechnicalAttributes