ISPPAC-CLK5320S-01TN64I ApplicationField
-Medical Equipment
-Cloud Computing
-Internet of Things
-Artificial Intelligence
-Industrial Control
-Wireless Technology
-5G Technology
-Consumer Electronics
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ISPPAC-CLK5320S-01TN64I FAQ Chips
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ICs ISPPAC-CLK5320S-01TN64I Features
• Zero delay buffer
• Non-zero delay buffer with output divider
• Clock A/B selection multiplexer
• Programmable single-ended output standards and individual enable controls
■ Up to Three Clock Frequency Domains
• Programmable on-chip loop filter
■ Fully Integrated High-Performance PLL
– Locked to VCO frequency
■ Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges
• Programmable termination
(Skew) Per Output
■ Up to 20 Programmable Fan-out Buffers
• Dual non-zero delay buffer
• Up to +/- 5ns skew range
– 40 to 70Ω in 5Ω increments
• Programmable single-ended or differential input reference standards
• Coarse and fine adjustment modes
– LVTTL, LVCMOS, SSTL, HSTL, LVDS,
• 8 settings; minimum step size 156ps
• Compatible with spread spectrum clocks
• Programmable Feedback Standards
– LVTTL, LVCMOS, HSTL, eHSTL, SSTL
■ Low Jitter Peak-to-Peak (< 70 ps)
■ Full JTAG Boundary Scan Test In-System Programming Support
– LVTTL, LVCMOS, SSTL, HSTL
■ Four Operating Configurations
– 1.5V, 1.8V, 2.5V, 3.3V
■ Flexible Clock Reference and External Feedback Inputs
■ Precision Programmable Phase Adjustment
■ 48-pin and 64-pin TQFP Packages
■ Low Output to Output Skew (<100ps)
• Internal/external feedback
• Zero delay and non-zero delay buffer
■ 8MHz to 267MHz Input/Output Operation
• Programmable slew rate
• Three “Power of 2” output dividers (5-bit)
LVPECL, Differential HSTL, Differential SSTL
• Up to 10 banks with individual VCCO and GND
■ All Inputs and Outputs are Hot Socket Compliant
• Programmable output impedance
• Programmable lock detect
■ Exceptional Power Supply Noise Immunity
Request ISPPAC-CLK5320S-01TN64I FPGA Quote, Pls Send Email to Sales@hillmancurtis.com Now
Xilinx ISPPAC-CLK5320S-01TN64I Overview
ISPPAC-CLK5320S-01TN64I Lattice Semiconductor Corporation, IC BUFFER FANOUT 20OUTPUT 64TQFP
Zero Delay Buffer 20-Out eHSTL/HSTL/LVCMOS/LVTTL/SSTL Single-Ended 64-Pin TQFP TrayClock Drivers & Distribution ISP 0 Delay Unv Fan- Out Buf-Sngl End I
The Lattice Clock & Timer ICs series ISPPAC-CLK5320S-01TN64I is Clock Drivers & Distribution ISP 0 Delay Unv Fan- Out Buf-Sngl End I, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
ISPPAC-CLK5320S-01TN64I Tags integrated circuit
1. ispPAC-CLK5320S evaluation board
2. ispPAC-CLK5320S reference design
3. ISPPAC-CLK5320S-01TN64I Datasheet PDF
4. ispClock 5300S evaluation kit
5. ispClock 5300S starter kit
6. Lattice ispClock 5300S development board
7. Lattice ispPAC-CLK5320S
8. ispClock 5300S ispPAC-CLK5320S
9. ispClock 5300S evaluation kit
Xilinx ISPPAC-CLK5320S-01TN64I TechnicalAttributes
-Maximum Operating Temperature + 85℃
-Mounting Style SMD/SMT
-Minimum Operating Temperature – 40℃
-Factory Pack Quantity 800
-Package / Case TQFP-64
-Packaging Tray
