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ISPPAC-POWR1208P1-01T44 FAQ Chips
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ICs ISPPAC-POWR1208P1-01T44 Features
■ Monitor and Control Multiple Power Supplies
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Xilinx ISPPAC-POWR1208P1-01T44 Overview
The Lattice ispPAC-POWR1208 incorporates both insystem programmable logic and
in-system programmable analog circuits to perform special functions for power
supply sequencing and monitoring. The ispPACPOWR1208 device has the capability
to be configured through software to control up to eight outputs for power
supply sequencing and 12 comparators monitoring supply voltage limits, along
with four digital inputs for interfacing to other control circuits or digital
logic. Once configured, the design is downloaded into the device through a
standard JTAG interface. The circuit configuration and routing are stored in
non-volatile E2 CMOS. PAC-Designer, an easy-to-use Windows-compatible software
package gives users the ability to design the logic and sequences that control
the power supplies or FET driver circuits. The user has control over timing
functions, programmable logic functions and comparator threshold values as well
as I/O configurations.
The ispPAC-POWR1208 device is specifically designed as a fully-programmable
power supply sequencing controller and monitor for managing up to eight separate
power supplies, as well as monitoring up to 12 analog inputs or supplies. The
ispPAC-POWR1208 device contains an internal PLD that is programmable by the user
to implement digital logic functions and control state machines. The internal
PLD connects to four programmable timers, special purpose I/O and the
programmable monitoring circuit blocks. The internal PLD and timers can be
clocked by either an internal programmable clock oscillator or an external clock
The voltage monitors are arranged as 12 independent comparators each
with 192 programmable trip point settings. Monitoring levels are set around the
following standard voltages: 1.2V, 1.5V, 1.8V, 2.5V, 3.3V or 5.0V.
voltages can be monitored simultaneously (i.e., continuous-time operation).
Other non-standard voltage levels can be accounted for using various scale
For added robustness, the comparators feature a variable hysteresis
that scales with the voltage they monitor. Generally, a larger hysteresis is
better. However, as power supply voltages get smaller, that hysteresis
increasingly affects trip-point accuracy. Therefore, the hysteresis is +/-16mV
for 5V supplies and scales down to +/-3mV for 1.2V supplies, or about 0.3% of
the trip point.
The programmable logic functions consist of a block of 36 inputs
with 81 product terms and 16 macrocells. The architecture supports the sharing
of product terms to enhance the overall usability. Output pins are configurable
in two different modes. There are eight outputs for controlling eight different
power supplies. OUT5-OUT8 are open-drain outputs for interfacing to other
circuits. The HVOUT1-HVOUT4 pins can be programmed individually as open-drain
outputs or as high voltage FET gate drivers. As high voltage FET gate driver
outputs, they can be used to drive an external N-Channel MOSFET as a switch to
control the voltage rampup of the target board. The four HVOUT drivers have
programmable current and voltage levels. Of the eight outputs, four can be
configured in the FET gate driver mode or open-drain digital mode.
ISPPAC-POWR1208P1-01T44 Tags integrated circuit
1. ispPAC-POWR starter kit
2. ISPPAC-POWR1208 development board
3. ISPPAC-POWR1208 reference design
4. Lattice ispPAC-POWR development board
5. Lattice ISPPAC-POWR1208
6. ISPPAC-POWR1208P1-01T44 Datasheet PDF
7. ispPAC-POWR ISPPAC-POWR1208
8. ispPAC-POWR evaluation kit
9. Lattice ispPAC-POWR development board
Xilinx ISPPAC-POWR1208P1-01T44 TechnicalAttributes