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ICs LCMXO2-4000HC-4FG484C2U Features
Flexible Logic Architecture
Request LCMXO2-4000HC-4FG484C2U FPGA Quote, Pls Send Email to Sales@hillmancurtis.com Now
Xilinx LCMXO2-4000HC-4FG484C2U Overview
The MachXO2 family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from
256 to 6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature
Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), preengineered source synchronous I/O support, advanced configuration support including dual-boot capability and
hardened versions of commonly used functions such as SPI controller, I2
C controller and timer/counter. These features allow these devices to be used in low cost, high volume consumer and system applications.
The MachXO2 devices are designed on a 65nm non-volatile low power process. The device architecture has several features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip PLLs and oscillators dynamically. These features help manage static and dynamic power consumption resulting in low
static power for all members of the family.
The MachXO2 devices are available in two versions – ultra low power (ZE) and high performance (HC and HE)
devices. The ultra low power devices are offered in three speed grades -1, -2 and -3, with -3 being the fastest. Similarly, the high-performance devices are offered in three speed grades: -4, -5 and -6, with -6 being the fastest. HC
devices have an internal linear voltage regulator which supports external VCC supply voltages of 3.3V or 2.5V. ZE
and HE devices only accept 1.2V as the external VCC supply voltage. With the exception of power supply voltage
all three types of devices (ZE, HC and HE) are functionally compatible and pin compatible with each other.
The MachXO2 PLDs are available in a broad range of advanced halogen-free packages ranging from the space
saving 2.5×2.5 mm WLCSP to the 23×23 mm fpBGA. MachXO2 devices support density migration within the same
package. Table 1-1 shows the LUT densities, package and I/O options, along with other key parameters.
The pre-engineered source synchronous logic implemented in the MachXO2 device family supports a broad range
of interface standards, including LPDDR, DDR, DDR2 and 7:1 gearing for display I/Os.
The MachXO2 devices offer enhanced I/O features such as drive strength control, slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pulldown and bus-keeper features are controllable on a “per-pin” basis.
A user-programmable internal oscillator is included in MachXO2 devices. The clock output from this oscillator may
be divided by the timer/counter for use as clock input in functions such as LED control, key-board scanner and similar state machines.
The MachXO2 devices also provide flexible, reliable and secure configuration from on-chip Flash memory. These
devices can also configure themselves from external SPI Flash or be configured by an external master through the
JTAG test access port or through the I2
C port. Additionally, MachXO2 devices support dual-boot capability (using
external Flash memory) and remote field upgrade (TransFR) capability.
LCMXO2-4000HC-4FG484C2U Tags integrated circuit
1. MachXO2 starter kit
2. LCMXO2-4000 evaluation board
3. MachXO2 evaluation kit
4. MachXO2 LCMXO2-4000
5. LCMXO2-4000HC-4FG484C2U Datasheet PDF
6. Lattice LCMXO2-4000
7. LCMXO2-4000 development board
8. LCMXO2-4000 reference design
9. MachXO2 LCMXO2-4000
Xilinx LCMXO2-4000HC-4FG484C2U TechnicalAttributes
-Supplier Device Package 484-FPBGA (23×23)
-Total RAM Bits 94208
-Number of I/O 278
-Mounting Type Surface Mount
-Number of LABs/CLBs 540
-Number of Logic Elements/Cells 4320
-Operating Temperature 0℃ ~ 85℃ (TJ)
-Voltage – Supply 2.375V ~ 3.465V
-Package / Case 484-BBGA