LCMXO2-4000HC-6QN84I ApplicationField
-Internet of Things
-Wireless Technology
-Medical Equipment
-Cloud Computing
-5G Technology
-Consumer Electronics
-Industrial Control
-Artificial Intelligence
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LCMXO2-4000HC-6QN84I FAQ Chips
Q: How can I obtain software development tools related to the Lattice FPGA platform?
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ICs LCMXO2-4000HC-6QN84I Features
Flexible Logic Architecture
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Xilinx LCMXO2-4000HC-6QN84I Overview
The MachXO2 family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from 256 to 6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), pre-engineered source synchronous I/O support, advanced configuration support including dual-boot capability and hardened versions of commonly used functions such as SPI controller, I2C controller and timer/counter. These features allow these devices to be used in low cost, high volume consumer and system applications.The MachXO2 devices are designed on a 65 nm non-volatile low power process. The device architecture has several features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip PLLs and oscillators dynamically. These features help manage static and dynamic power consumption resulting in low static power for all members of the family.The MachXO2 devices are available in two versions – ultra low power (ZE) and high performance (HC and HE) devices. The ultra low power devices are offered in three speed grades –1, –2 and –3, with –3 being the fastest. Similarly, the high-performance devices are offered in three speed grades: –4, –5 and –6, with –6 being the fastest. HC devices have an internal linear voltage regulator which supports external VCC supply voltages of 3.3 V or 2.5 V. ZE and HE devices only accept 1.2 V as the external VCC supply voltage. With the exception of power supply voltage all three types of devices (ZE, HC and HE) are functionally compatible and pin compatible with each other.The MachXO2 PLDs are available in a broad range of advanced halogen-free packages ranging from the space saving 2.5 mm x 2.5 mm WLCSP to the 23 mm x 23 mm fpBGA. MachXO2 devices support density migration within the same package. Table 1-1 shows the LUT densities, package and I/O options, along with other key parameters.The pre-engineered source synchronous logic implemented in the MachXO2 device family supports a broad range of interface standards, including LPDDR, DDR, DDR2 and 7:1 gearing for display I/Os.The MachXO2 devices offer enhanced I/O features such as drive strength control, slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-down and bus-keeper features are controllable on a “per-pin” basis.A user-programmable internal oscillator is included in MachXO2 devices. The clock output from this oscillator may be divided by the timer/counter for use as clock input in functions such as LED control, key-board scanner and similar state machines.The MachXO2 devices also provide flexible, reliable and secure configuration from on-chip Flash memory. These devices can also configure themselves from external SPI Flash or be configured by an external master through the JTAG test access port or through the I2C port. Additionally, MachXO2 devices support dual-boot capability (using external Flash memory) and remote field upgrade (TransFR) capability.Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the MachXO2 family of devices. Popular logic synthesis tools provide synthesis library support for MachXO2. Lattice design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route the design in the MachXO2 device. These tools extract the timing from the routing and back-annotate it into the design for timing verification.Lattice provides many pre-engineered IP (Intellectual Property) LatticeCORE™ modules, including a number of reference designs licensed free of charge, optimized for the MachXO2 PLD family. By using these configurable soft core IP cores as standardized blocks, users are free to concentrate on the unique aspects of their design, increasing their productivity. Jotrin Electronics is an authorized Lattice Semiconductor distributor.
The Lattice FPGAs (Field Programmable Gate Array) series LCMXO2-4000HC-6QN84I is IC FPGA 68 I/O 84QFN, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
LCMXO2-4000HC-6QN84I Tags integrated circuit
1. MachXO2 evaluation kit
2. Lattice MachXO2 development board
3. LCMXO2-4000 evaluation board
4. LCMXO2-4000 development board
5. Lattice LCMXO2-4000
6. MachXO2 LCMXO2-4000
7. MachXO2 starter kit
8. LCMXO2-4000 reference design
9. LCMXO2-4000 development board
Xilinx LCMXO2-4000HC-6QN84I TechnicalAttributes
-Product MACHXO2
-Distributed RAM 34 kbit
-Number of Logic Elements 4320
-Embedded Block RAM – EBR 92 kbit
-Mounting Style SMD/SMT
-Series LCMXO2
-Number of I/Os 68 I/O
-Product Type FPGA – Field Programmable Gate Array
-Moisture Sensitive Yes
-Subcategory Programmable Logic ICs
-Operating Supply Voltage 2.5 V/3.3 V
-Minimum Operating Temperature – 55 C
-Maximum Operating Temperature + 125 C
-Standard Pack Qty 260
-Tradename MachXO2
