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ICs LCMXO3D-4300HC-6BG256I Features
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Xilinx LCMXO3D-4300HC-6BG256I Overview
The MachXO3D device family is the next generation of Lattice Semiconductor Low Density PLDs including enhanced
security features and on-chip dual boot flash. The enhanced security features include Advanced Encryption Standard
(AES) AES-128/256, Secure Hash Algorithm (SHA) SHA-256, Elliptic Curve Digital Signature Algorithm (ECDSA), Elliptic
Curve Integrated Encryption Scheme (ECIES), Hash Message Authentication Code (HMAC) HMAC-SHA256, Public Key
Cryptography, and Unique Secure ID. The MachXO3D family is a Root-of-Trust hardware solution that can easily scale to
protect the whole system with its enhanced bitstream security and user mode functions. MachXO3D device provides
breakthrough I/O density with high number of options for I/O programmability. The device I/O features the support for
latest industry standard I/O, including programmable slew-rate enhancements and I3C support.
The MachXO3D family of low power, instant-on, Flash based PLDs have two devices with densities of 4300 and 9400
Look-Up Tables (LUTs). MachXO3D devices include on-chip dual boot configuration flash as well as multi-sectored User
Flash Memory (UFM). In addition to LUT-based programmable logic, these devices feature Embedded Block RAM (EBR),
Distributed RAM, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O support, advanced configuration
support including on-chip dual-boot capability and hardened versions of commonly used functions such as SPI
controller, I2C controller, and timer/counter.
The MachXO3D devices are designed on a 65-nm non-volatile low power process. The device architecture has several
features such as programmable low swing differential I/O and the ability to turn off I/O banks, on-chip PLLs and
oscillators dynamically. These features help manage static and dynamic power consumption resulting in low power for
all members of the family.
The MachXO3D devices are available in two performance levels: ultra low power (ZC) and high performance (HC). The
ultra low power devices are offered in two speed grades: –2 and –3, with –3 being the fastest. Similarly, the
high-performance devices are offered in two speed grades: –5 and –6, with –6 being the fastest. ZC/HC devices have an
internal linear voltage regulator, which supports external VCC supply voltages of 3.3 V or 2.5 V. With the exception of
power/performance profiles, the two types of devices, ZC and HC, are pin compatible with each other.
The MachXO3D PLDs are available in a broad range of advanced halogen-free packages ranging from the space saving
10 x 10 mm QFN to the 19 x 19 mm caBGA. MachXO3D devices support density migration within the same package.
The MachXO3D devices offer enhanced I/O features such as drive strength control, finer slew rate control, I3C
compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs, and hot socketing. Pull-up,
pull-down, and bus-keeper features are controllable on a per-pin basis.
A user-programmable internal oscillator is included in MachXO3D devices. The clock output from this oscillator may be
divided by the timer or counter for use as clock input in functions such as LED control, key-board scanner, and similar state
The MachXO3D devices also provide flexible, reliable, and secure configuration from on-chip Flash with the encryption
and authentication options. These devices can also configure themselves from external SPI Flash or be configured by an
external master through the JTAG test access port or through the SPI/I2C port. Additionally, MachXO3D devices support
on-chip dual-boot capability to reduce the system cost and remote field upgrade TransFR capability.
Lattice Semiconductor provides a variety of design tools that allow complex designs to be efficiently implemented using
the MachXO3D family of devices. Popular logic synthesis tools provide synthesis library support for MachXO3D devices.
Lattice design tools use the synthesis tool output along with the user-specified preferences and constraints to place
and route the design in the MachXO3D device. These tools extract the timing from the routing and back-annotate it
into the design for timing verification.
Lattice Semiconductor provides many pre-engineered Intellectual Property (IP) LatticeCORETM modules, including a
number of reference designs licensed free of charge, optimized for the MachXO3D PLD family. By using these
configurable soft core IP cores as standardized blocks, you are free to concentrate on the unique aspects of their
design, increasing their productivity.
LCMXO3D-4300HC-6BG256I Tags integrated circuit
1. LCMXO3D-4300 development board
2. Lattice MachXO3D development board
3. MachXO3D LCMXO3D-4300
4. LCMXO3D-4300 reference design
5. Lattice LCMXO3D-4300
6. LCMXO3D-4300HC-6BG256I Datasheet PDF
7. MachXO3D starter kit
8. LCMXO3D-4300 evaluation board
9. LCMXO3D-4300 reference design
Xilinx LCMXO3D-4300HC-6BG256I TechnicalAttributes