The Xilinx Spartan-II FPGA Family offers users lots of logic resources, high performance, and rich features at a very low price. It is a six-member family offering densities with system gates between 15,000 – 200,000. The system performance has a support up to about 200 MHz. Its major features include a block RAM of 56K bits, RAM distributed to 75,264 bits, four DLLs, and 16 I/O standards. It has predictable and fast interconnects, which means that design iterations that are successive keeps meeting timing requirements.
Also, the Xilinx Spartan-II FPGA Family is a much better option to ASICs. The FPGA prevents the long development cycles, initial cost and the inherent risk involved with conventional ASICs.
Furthermore, the programmability of FPGA allows for upgrades to the design in fields not requiring the replacement of hardware. This is not possible with ASICs.
Features of the Xilinx Spartan-II FPGA Family
The 2nd generation replacement technology for ASIC has the following features
- Cost is very low
- Reprogrammability is unlimited
- Features are streamlined based on the architecture of the Virtex® FPGA
- High densities up to 5,292 logic cells. It also features about 200,000 system gates
- It is cost effective, with a micron process of 0.18
The System Level has the following features
- The hierarchical memory of the SelectRAM™ has a distributed RAM of 16 bits/LUT. Also, the interfaces to the external RAM are fast, and the bit block RAM is configurable
- 100% PCI compliant
- The routing architecture is segmented and works with low power
- Complete readback ability to ensure observability/verification
- Cascade chain that ensures wide-input functions
- Great multiplier support
- Carry logic is dedicated to ensure high-speed arithmetic
- Many latches/registers with reset, set, enable
- Four primary global low-skew nets for clock distribution
- Four DLLs dedicated to ensuring better clock control
- Boundary scan logic is IEEE 1149.1 compatible
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Versatile packaging and input/output
- Compact Hot swap PCI friendly
- Package options that are lead-free
- There are low-cost packages in virtually all densities
- Compatibility of family footprint in usual packages
- 16 interface standards with high-performance
- Hold time of zero explains system timing
The powering of the main logic is at 2.5V,
- The powering of the Input/Output is at 3.3V, 2.5V or 1.5V.
It has the full support of the development system of the strong Xilinx® ISE®
- Routing, placement, and mapping is fully automatic
General Overview of the Xilinx Spartan-II FPGA Family
The Xilinx Spartan-II FPGA Family features a programmable, flexible, regular architecture of CLBs – Configurable Logic Blocks. Programmable I/O blocks surround these CLBs. Four DLLs (Delay-Locked Loops) are present at each of the die’s corners.
Also, there are two block RAM columns lying on the die’s opposite sides. These opposite sides are found between the IOB columns and the CLBs. A strong hierarchy of routing channels interconnects these elements.
It is possible to customize the Xilinx Spartan-II FPGA Family. You do this by loading the configuration data in the static internal memory cells. Also, it is possible to achieve countless reprogramming cycles using this approach.
Furthermore, these cells stored values help in determining login interconnections and functions, which the FPGA implements. You can read the configuration data from the serial PROM. Furthermore, you can also write in the FPGA in boundary scan, slave parallel or slave serial modes.
The Xilinx Spartan-II FPGA Family are useful in applications requiring high volume whereby a quick programmable solution’s versatility adds benefits. Furthermore, this family is best for reducing the development cycles of products coupled with providing a solution that is cost-effective for all high-volume productions.
In addition, the Xilinx Spartan-II FPGA Family achieves low-cost, high-performance operation. This is possible through its advanced semiconductor technology and architecture. Also, with Xilinx Spartan-II devices, you can get system clock rates of about 200 MHz. Asides from the conventional benefits that this programmable high-volume logic solutions offers, the Xilinx Spartan-II FPGA Family provides synchronous on-chip dual-port and single-port RAM (both in distributed and block). Other features include drivers for DLL clock, programmable reset and set on the flip-flops, quick carry logic, etc.
The Functional Description of the XILINX Spartan-II FPGA Family
Architectural Description
The Spartan-II FPGA Array
The FPGA is Spartan-II refers to a field-programmable gate. The Spartan-II FPGA array features five configurable elements which are:
- Block RAM memories with 4096 bits each
- CLBs offer the elements for building most logic
- Flexible multi-level interconnect structure
- The clock DLLs delay clock domain control
- IOBs offer the interface needed between the internal logic and package pins
The CLBs create the central logic structure having access to all routing structures. The memory and logic elements are around the IOBs. Also, this helps to route signals easily on and off the chip. Values in the static memory cells are in charge of the interconnect sources and logic elements. These values can reload to alter the function of the device.
Input/Output Block
There are inputs and outputs on the Spartan-II FPGA IOB. These two elements support various I/O signaling standards. Furthermore, the outputs and inputs can support different modern memory and bus interfaces. The three IOB registers perform as level-sensitive latches or edge-triggered D-type flip flops.
Every IOB features a Clock Enable (CE) signal for every register. Also, the IOB features a Clock Signals (CLK) distributed across the three registers. Apart from the CE and CLK control signals, there is a Set/Reset (SR) shared by the three registers.
This signal can be easily configured as an asynchronous Preset, a synchronous Reset, asynchronous Clear, and a synchronous Set. Furthermore, polarity control is a feature controlled by the software. All the control signals in IOB feature independent polarity controls. The input and output buffers are also not left out.
Also, there are pull-down and pull-up resistors that can be independently attached to each pad. A weak-keeper circuit can be also attached to each pad. All outputs that don’t partake in configuration will forcefully remain in a high-impedance state. The weak-keeper circuits and pull-down resistors remain inactive. However, inputs may pull up optionally.
Furthermore, the configuration mode pins control the pull-up resistor’s activation before configuration. All pins will stay afloat if pull-up resistors don’t activate. There must be external pull-down or pull-up resistors on pins needed to be at a specific logic level. This must happen before any configuration.
Also, it is important to protect pads against any damage from electrostatic discharge. Also, protecting pas from over-voltage transients is crucial. There are two types of over-voltage protection. These are the 5v compliance and no 5V compliance. The 5V compliance permits a structure connected to the ground to turn on when output increases up to 6.5V. In some cases, 5V compliance isn’t necessary.
Input Path
The Spartan-II FPGA IOB input path features a buffer. This routes the input signal to internal logic. Also, the buffer can route the input signal via an optional input flip-flop. Furthermore, the D-input path features an optional delay element that removes pad-to-pad hold time. The delay must match be compatible with the FPGA’s internal clock-distribution delay.
You can configure each input buffer to comply with the low-voltage signaling standards. The input buffer uses a threshold voltage (VREF) in some of these standards. The demand for VREF restricts using standards in proximity to each other. After configuration, there are optional pull-down and pull-up resistors at every input.
Output Path
This comprises a 3-state output buffer that conveys the output signal onto the pad. The output’s 3-state control can route directly from the internal logic. Also, the output signal can route to the buffer via an optional IOB output flip-flop.
Every output driver can be independently programmed for various low-voltage signaling standards. Also, the externally supplied Vcco voltage determines the output high voltage. The demand for Vcco restricts the use of standards in proximity to each other.
I/O Banking
Some I/O standards need Vcco or VREF voltages. These voltages connect externally to device pins. Furthermore, there are restrictions on the type of I/O standards to combine in a specific bank. There are eight I/O banks due to the separation of each edge of the FPGA in two banks. Every bank features several Vcco pins which must connect to the same voltage. The output standards will determine the voltage.
A combination of output standards can occur within a bank. This happens if they utilize a similar Vcco. All VREF pins must connect o the external voltage source. Also, in a bank, inputs demanding VREF can combine with those that don’t. However, just one VREF voltage is ideal for use within a bank.
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Configurable Logic Block
The logic cell (LC) is the main building block of the Spartan-II FPGA CLB. An LC comprises a storage element, a 4-input function generator, and a carry logic. Each Spartan-II FPGA CLB features four LCs. Also, the FPGA CLB comprises logic that works with function generators. This helps to offer about six inputs.
Storage elements
You can configure these elements as level-sensitive latches or edge-triggered D-type flip flops. The function generators within the slice can drive the D inputs. Also, each slice features synchronous reset and set signals.
Furthermore, the Synchronous set forceful allows a storage element into the specified initialization state for it. The F6 multiplexer selects one of the F5-multiplexer outputs. It then uses this to combine the outputs of the CLB’s four function generators. This allows the use of any 6-input function.
Each CLB features four feedthrough paths. These paths offer additional data input lines that don’t use up logic resources.
Additional logic
The F5 multiplexer in every slice mixes the function generator outputs. This offers a function generator that can make use of 5-inout function or a 4:1 multiplexer.
Arithmetic Logic
Carry logic can carry out high-speed arithmetic functions. The FPGA CLB provides support for two distinct carry chains. The carry chains have a height of two bits per CLB. Also, the arithmetic logic features an XOR gate. This enables the implementation of 1-bit full adder within an LC. Furthermore, an AND fate enhances the functionality of multiplier implementation. The carry path can cascade function generators for using wide logic functions.
Look-up Tables (LUT)
The function generators in Spartan-II FPGA are used as 4-input look-up tables. Every LUT can offer a 16 x 1-bit synchronous RAM. Also, you can combine the two LUTs in a slice to form a 32 x 1-bit or 16 x 2-bit synchronous RAM.
The LUT in Spartan-II FPGA can offer a 16-bit shift register. This can help to capture burst-mode or high-speed data. Also, you can use this mode to save up data in applications like Digital Signal Processing.
Block RAM
There are multiple large block RAMs incorporated by Spartan-II FPGAs. This helps to complement the RAM LUTs that offer shallow memory structures in CLBs. Block RAM memories are in columns. Spartan-II devices feature two columns. Each of the columns is along each vertical edge. These columns help to expand the chip’s full height. A Spartan-II device with a height of eight CLBs will feature two memory blocks for each column.
Programmable Routing Matrix
This delay path restricts the speed of any worst-case design. The routing architecture and the place and route software were defined in a single process. This process reduces long-path delays and provides the best system performance. Also, it reduces compilation times since the architecture is user-friendly.
Global Routing
This distributes signals with high fanout throughout the device. Spartan-II devices feature two tiers of global routing resources. These are secondary and primary global routing resources. There are four dedicated global nets with input pins in the primary global routing resources.
Each global clock net can drive IOB and CLB. Also, it can block clock pins. Global buffers can only drive these nets. There is one global buffer for every global net.
There are 24 backbone lines in secondary global routing resources. Furthermore, there are 12 backbone lines across the bottom of the chip and 12 across the top. The secondary global resources aren’t limited to routing only clock pins. Therefore, they are more flexible than the primary resources.
General Purpose Routing
The majority of Spartan-II FPGA signals route on the general purpose routing. Most interconnect resources are specifically connected with this routing hierarchy. The general routing resources are vertical and horizontal routing channels associated. Below are the general-purpose routing resources:
A general routing matrix (GRM) is adjacent to every CLB. Vertical and horizontal resources connect through the GRM. Also, the GRM serves as the means through which the CLB accesses the general purpose routing.
GRM signals are well routed by 96 buffered Hex lines to other Grams six blocks. Hex lines are in a staggered pattern. Also, you can only access Hex lines at the midpoint or endpoint.
About 33 % of hex lines are bidirectional while the rest are without direction.
Dedicated Routing
Some signals need dedicated routing resources to enhance their performance. The dedicated routing resources are majorly for two types of signals. Horizontal routing resources are for on-chip busses. There are four partitionable bus lines for each CLB row. This allows several busses within a row. Two dedicated nets for each CLB propagate transmit signals to the adjacent CLB.
Xilinx Spartan-II FPGA Family Design Considerations
Output Drive Source Voltage (VCCO) Pins
The majority of the low voltage Input/Output standards which has the backing of the versatile I/Os need a different source voltage for the output drive (VCCO).This leads to each device having to support many VCCOs multiple source voltages for the output drive.
For some of the packages, the supplies of the VCCO supplies are tied internally together. The PQ208 and VQ100 offer one combined supply of VCCO. Furthermore, the CS144 and the TQ144 packages offer four VCCO supplies that are independent. Also, the FG456 and FG256 offer eight VCCO supplies that are independent.
All output buffers that fall within a specific VCCO bank has to share a similar voltage for the output drive source. The input buffers for the PCI 66_3, LVCMOS2, LVTTL, and PCI33_3, makes use of the VCCO voltage.
Reference Voltage Pins
The low-voltage Input/Output standards having a differential input buffer usually need an input VREF (reference voltage). The VREF is provided as the device’s external signal.
This reference voltage signal is within the device such that all the packages in there are about eight internal VREF banks. In each of the VREF banks about one out of every six Input/Output pins is configured automatically as an input for the reference voltage.
Within each of the VREF banks, all input buffers requiring a VREF signal has to be the same or similar type. You can place output and input buffers of all types without the need of a reference voltage.
Effects of the Transmission Line
An electrical signal’s delay along a specific wire is being dominated by the fall and rise times when the distance covered by the signal is a short one. Delays of the transmission line vary with capacitance and inductance. However, with boards that are well-designed you can see delays of about 180 ps for every inch.
The reflections or effects of the transmission line typically begin at 1.5″ for the fast rise & fall times. Non-existent or poor changes or termination in the impedance of the transmission line can result in extra delays in much longer traces.
As the speed of the system keeps increasing, the effect from the Input/Output delays could transform into a limiting factor. Therefore, the termination of the transmission line becomes more significant.
Techniques for Termination
Different termination techniques help in reducing the impact of the effects of the transmission line. The techniques below are for output termination.
- Series
- None
- Parallel and Series (Series-Shunt)
- Parallel (Shunt)
The below are the techniques for input termination.
- Parallel (Shunt)
- None
Note that you can apply any of the termination techniques in your preferred combination.
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Guidelines for Simultaneous Switching
It is possible for ground bounce to happen with digital Integrated circuits working with high speed, when there is a change in the state of multiple outputs simultaneously, thereby leading to the internal logic or output having an unwanted transient behavior. You can also refer to this problem as the SSO – Simultaneous Switching Output problem.
The major cause of ground bounce is as a result of the present changes in the accumulated inductance of ground metallization, bond wires, and ground pins. There is a deviation in the internal ground level of the integrated circuit from the ground level of the external system. This happens just for a short time (a few nano secs) after a simultaneous change in the state of multiple outputs.
Ground bounce has an effect on any input and stable outputs. This is because it gives interpretations of the incoming signal. It achieves this by drawing some comparison between it and the internal ground. Also, if the amplitude of the ground bounce surpasses the actual noise margin (instantaneous), then you can interpret a non-changing input as a pulse having a polarity that is opposite to the ground’s bounce.
The Xilinx Spartan-II FPGA Family Devices
The Xilinx Spartan-II FPGA Family devices include the following.
XC2S50-TQG144C XC2S50-6TQG144C XC2S50-5TQG144I XC2S50-5TQG144C XC2S50-5TQ144I XC2S50-5TQ144C
XC2S50-5PQG208I XC2S50-5PQG208C XC2S50-5PQ208C XC2S50-5FGG256I XC2S50-5FGG256C XC2S50-5FG256I
XC2S30-VQ100AMS XC2S30-PQ208 XC2S30-6VQG100C XC2S30-6TQG144C XC2S30-6CS144C XC2S30-5VQG100C
XC2S30-5VQ100I XC2S30-5VQ100C XC2S30-5TQG144I XC2S30-5TQG144C XC2S30-5PQ208C XC2S30-5CSG144C
XC2S200-6FGG456C XC2S200-6FGG256C XC2S200-5PQG208C XC2S200-5PQ208C XC2S200-5FGG456I XC2S200-5FGG456C
XC2S200-5FGG256I XC2S200-5FGG256C XC2S200-5FG456I XC2S200-5FG456C XC2S200-5FG256I XC2S15-5VQG100I
XC2S15-5TQG144C XC2S150-6PQ208C XC2S150-5PQG208I XC2S150-6PQG208C XC2S15-5VQG100C XC2S15-5VQ100C
XC2S150-5FG256C XC2S150-5FG456C XC2S100-6PQG208C XC2S100-6PQ208I XC2S150-5PQG208C XC2S150-5PQ208Q
XC2S100-6PQG208I XC2S150-5PQ208I XC2S100-5TQG144I XC2S100-6PQ208C XC2S100-5TQ144C XC2S100-5TQ144I
XC2S100-5PQG208I XC2S100-5PQ208I XC2S100-5FGG256I XC2S100-5FGG256C XC2S100-5FG256C XC2S100-5FG256I
XC2S30-VQG100AMS XC2S200-5FG456-I XC2S100-5FG456CES XC2S50-FG256AMS XC2S50-6TQ144C XC2S50-6PQG208C
XC2S50-6FGG256C XC2S50-6PQ208C XC2S50-6FG256C XC2S50-5PQ208I XC2S30-CS144AMS XC2S50-5FG256C
XC2S30-6TQ144C XC2S30-6VQ100C XC2S30-6CSG144C XC2S30-5VQG100I XC2S30-5TQ144I XC2S30-5TQ144C
XC2S30-5CSG144I XC2S30-5CS144I XC2S30-5CS144C XC2S200-PQ208AMS XC2S200-6PQG208C XC2S200-6PQ208C
XC2S200-6FG456C XC2S200-6FG256C XC2S200-5PQG208I XC2S200-5PQ208I XC2S200-5FG256FC XC2S200-5FG256C
XC2S15-6VQG100C XC2S15-6VQ100C XC2S15-6TQG144C XC2S15-6TQ144C XC2S15-5VQ100I XC2S15-5TQG144I
XC2S15-5TQ144I XC2S15-5TQ144C XC2S15-5CS144I XC2S15-5CS144C
Conclusion
By now, you should have gained vast knowledge as regards the Xilinx Spartan-II FPGA Family. They come with great features and involve about 100 family devices. However, if after going through you have some questions on your mind, you are free to ask us here. We are always here to help you.
