Xilinx Universal PLD

What are the Features, Devices, and the Functional Description of the Xilinx Universal PLD?

The  XCR22V10  can be regarded as the first-ever  SPLD that could combine  low power with high performance, without requiring “turbo bits” as well as other power down alternatives or schemes.  For Xilinx to make this happen, they utilized the FZP technique for design. Also, this technique helps in replacing the methods for the conventional sense amplifier, useful for the implementation of product terms. Note that this technique has been useful in PLDs from the bipolar era, featuring a chain of CMOS gates.

Eventually, this leads to the combining of high speed and low power, which has initially been unachievable during the PLD arena. Also, to achieve 3V operation, the Xilinx provides the XCR22LV10, which delivers low power and high speed in a 3V implementation.

Furthermore, the XCR22V10 utilizes the well-known logic array structure (AND/OR) that permits the direct implementation of equations regarding sum-of-products. The device features an AND array that is programmable and it drives an OR array that is fixed.

In addition, the XCR22V10 executes logic functions as expressions of sum-of-products in a fixed-OR/programmable-AND logic array. The creation of functions that are user-defined happens via the programming of input signals’ connections in the array.

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What is a Programmable Logic Device (PLD)?

 

Programmable logic devices are electronic components utilized in building digital circuits that are reconfigurable. In contrast to integrated circuits that are composed of logic gates, as well as having a unique and fixed function, during the manufacture time, the functions of PLDs are not defined. Also, before you can use the PCB in a circuit, then you have to reconfigure or program it making use of a specific program.

Ways in which Programmable Logic Devices retain their configuration

PLDs combine a memory device with a logic one. This memory is useful in the storage of a pattern, which was given during the programming of the chip. Majority of the data storage methods in integrated circuits have proven useful for PLDs. These are:

  • SRAM (static RAM)
  • Silicon antifuses
  • Flash memory
  • EEPROM or EPROM memory cells

SRAM

SRAM, which is also known as static RAM, can be seen as a volatile memory. What this means is that anytime you switch off the power, it loses its contents. PLDs that are SRAM-based will need reprogramming any time you switch on the circuit. You can achieve this automatically by a different section of the circuit.

Silicon Antifuses

These are connections, which are made via the application of voltages across a silicon area in the chip. We refer to these as antifuses because of their ability to function oppositely compared to the normal ones that start life like connections till electric current breaks them.

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Flash Memory

Furthermore, the flash memory is not volatile. It retains its contents completely even if you decide to switch off the power. Its storage is usually on MOSFET memory cells (floating gate). Furthermore, if you desire you can erase and reprogram it.

EEPROM or EPROM memory cells

EPROM memory cells are metal-oxide semiconductor transistors, which you can switch on just by the permanent trapping of a specific electric charge on its electrode. In addition, you will need a PAL programmer to achieve this. Also, this charge stays for years to come and you can only remove it when you expose it in a specific device called EPROM eraser and to a strong U.V light.

 

This is why it is very important in PLDs, which you need to reprogram from time to time like PLDs utilized in prototypes. Also, flash memory can be seen as an EEPROM holding information making use of electric charges that are trapped, just like in the case of EPROM. Furthermore, the flash memory has the ability to hold the information for many years; however, this cannot be as long as that of EPROM.

 

Looking back at 2005, the majority of CPLDs are erasable and programmable electrically, as well as non-volatile. One reason for this is that they are just too small to speak for the inconvenience that internal SRAM cells programming pose anytime they start up. Also, the cells of EPROM are costlier, as a result of its ceramic package having a quartz window.

Programming Languages of the PLD

The majority of devices using PAL programming allows input in standard file formats, which are known as ‘JEDEC files’. You can say they function just like software compilers. Languages utilized as the source code for the logic compilers are HDLs or hardware description languages.

 

CUPL, ABEL, and PALASM are frequently useful devices of low-complexity, while VHDL and Verilog are higher-level well-known description languages that serve very complex devices. ABEL is more limited, and is useful for historical purposes. However for any new designs, the VHDL is much more popular, with designs of low-complexity included.

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Advantages and Disadvantages of the Xilinx Universal PLD

Advantages of the Xilinx Universal PLD

  • Requires less power
  • Takes less time for design
  • High speed for switching
  • Low cost of development
  • Requires less space
  • Just the connection mask needs to be custom-made
  • Also, its circuit testing is easy
  • Adopting the new technology comes easy and quick
  • Design security is high
  • Furthermore, easy to modify the design
  • Very reliable
  • Logic designs that are time-consuming are absent
  • Design checking is easy
  • Very easy to change the design
  • Troubleshooting is easy
  • Simpler layout in contrast to other logic gate networks

Disadvantages of the Xilinx Universal PLD

  • It is a high-cost solution especially in very large quantities
  • Also, it is not flexible regarding integrating the analog box
  • Extra space requirements, power, additional cost, etc
  • No serious security
  • It requires large power
  • It requires a poor performance and a large area

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Devices of the Xilinx Universal PLD

The devices of the Xilinx Universal PLD are 22 in number. Let’s check them out

XCR22V10-10VO24I XCR22V10-10SO24I XCR22V10-10PC28I

XCR22V10-7SO24C XCR22V10-7VO24C XCR22V10-7VO24I

XCR22V10-7SO24 XCR22V10-10VO24C XCR22V10-7PC28C

XCR22V10-10SO24C XCR22LV10-15VO24I XCR22V10-10PC28C

XCR22LV10-15VO24C XCR22LV10-15SO24C XCR22LV10-15SO24I

XCR22LV10-15PC28I XCR22LV10-10VO24I XCR22LV10-15PC28C

XCR22LV10-10VO24C XCR22LV10-10SO24C XCR22LV10-10SO24I

XCR22LV10-10PC28C

Now let’s consider the features of some of these devices

XCR22V10-10VO24I

Features of the XCR22V10-10VO24I

  • The first-ever CMOS SPLD of the industry – features both the process technologies and CMOS design
  • The pin-to-pin delay of just 7.5 ns
  • A true device of Zero Power having no power down schemes or turbo bits
  • A static current below 75 µA
  • Its dynamic current is substantially lower than other competing devices
  • A design technique of Fast Zero Power, which offers high speed and very-low power
  • 24-pin SOIC
  • 24-pin TSOIC which utilizes 93% less space (in-system) in contrast to the 28-pin PLCC
  • More effective 0.5µ E2CMOS process
  • 1000 program cycles/erase guaranteed
  • Map of Function/JEDEC which works with UVCMOS, Bipolar, and EECMOS 22V10s
  • Also, this device is reprogrammable, making use of device programmers that are of industry standard
  • Many packaging alternatives that feature flow-through PCB friendly pinouts (TSSOP and SOL)
  • Ensured 20 years of data retention
  • Output polarity that is programmable
  • Asynchronous reset/synchronous preset capability
  • Electronic signature which aids identification
  • Security bit which helps in preventing any unauthorized access
  • Also present is the 28-pin PLCC having the JEDEC pinout, which is the standard
  • Present in industrial and commercial operating ranges
  • Design entry, as well as verification utilizing the CAE tools, which are the standards of the industry

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XCR22V10-10SO24I

Features of XCR22V10-10SO24I

  • A true device of Zero Power having no power down schemes or turbo bits
  • Its dynamic current is substantially lower than other competing devices
  • More effective 0.5µ E2CMOS process
  • The first-ever CMOS SPLD of the industry – features both the process technologies and CMOS design
  • The pin-to-pin delay of just 7.5 ns
  • A design technique of Fast Zero Power, which offers high speed and very-low power
  • 24-pin SOIC
  • Also, this device is reprogrammable, making use of device programmers that are of industry standard
  • Present in industrial and commercial operating ranges
  • 1000 program cycles/erase guaranteed
  • Electronic signature which aids identification
  • Ensured 20 years of data retention
  • Output polarity that is programmable
  • Security bit which helps in preventing any unauthorized access

XCR22V10-10PC28I

Features of the XCR22V10-10PC28I

  • The pin-to-pin delay of just 7.5 ns
  • A design technique of Fast Zero Power, which offers high speed and very-low power
  • 24-pin SOIC
  • Ensured 20 years of data retention
  • Output polarity that is programmable
  • Also, this device is reprogrammable, making use of device programmers that are of industry standard
  • Present in industrial and commercial operating ranges
  • Also, you can be sure of 1000 program cycles/erase
  • A true device of Zero Power having no power down schemes or turbo bits
  • The first-ever CMOS SPLD of the industry – features both the process technologies and CMOS design
  • Electronic signature which helps easy identification
  • Its dynamic current is substantially lower than other competing devices
  • More and better effective 0.5µ E2CMOS process
  • Security bit which helps in preventing any unauthorized access

XCR22V10-7SO24C

Features of XCR22V10-7SO24C

  • Map of Function/JEDEC which works with UVCMOS, Bipolar, and EECMOS 22V10s
  • Also, this device is reprogrammable, making use of device programmers that are of industry standard
  • Design entry, as well as verification utilizing the CAE tools, which are the standards of the industry
  • A true device of Zero Power having no power down schemes or turbo bits
  • A static current below 75 µA
  • Its dynamic current is substantially lower than other competing devices
  • The first-ever CMOS SPLD of the industry – features both the process technologies and CMOS design
  • A design technique of Fast Zero Power, which offers high speed and very-low power
  • 24-pin TSOIC which utilizes 93% less space (in-system) in contrast to the 28-pin PLCC
  • Present in industrial and commercial operating ranges
  • Asynchronous reset/synchronous preset capability
  • Electronic signature which aids identification

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XCR22V10-7VO24C

Features of XCR22V10-7VO24C

  • Security bit which helps in preventing any unauthorized access
  • 1000 program cycles/erase guaranteed
  • Electronic signature which aids identification
  • More effective 0.5µ E2CMOS process
  • The first-ever CMOS SPLD of the industry – features both the process technologies and CMOS design
  • Also, it features a pin-to-pin delay of just 7.5 ns
  • Output polarity that is programmable
  • A design technique of Fast Zero Power, which offers high speed and very-low power
  • 24-pin SOIC
  • This is a true device of Zero Power that neither has any power down schemes nor turbo bits
  • Furthermore, its dynamic current is substantially lower than other competing devices
  • Also, this device is reprogrammable, making use of device programmers that are of industry standard
  • You can find this in both industrial and commercial operating ranges
  • Ensured 20 years of data retention

XCR22V10-7VO24I

Features of XCR22V10-7VO24I

  • The pin-to-pin delay of just 7.5 ns
  • A true device of Zero Power having no power down schemes or turbo bits
  • Its dynamic current is substantially lower than other competing devices
  • A design technique of Fast Zero Power, which offers high speed and very-low power
  • Ensured 20 years of data retention
  • More effective 0.5µ E2CMOS process
  • Also, this device is reprogrammable, making use of device programmers that are of industry standard
  • 1000 program cycles/erase guaranteed
  • Electronic signature which aids identification
  • Security bit which helps in preventing any unauthorized access
  • Asynchronous reset/synchronous preset capability
  • Present in industrial and commercial operating ranges
  • Design entry, as well as verification utilizing the CAE tools, which are the standards of the industry

XCR22V10-7SO24

Features of XCR22V10-7SO24

  • 1000 program cycles/erase guaranteed
  • The first-ever CMOS SPLD of the industry – features both the process technologies and CMOS design
  • Also, it features a pin-to-pin delay of just 7.5 ns
  • Security bit which helps in preventing any unauthorized access
  • Output polarity that is programmable
  • Also, you are sure of 20 years of data retention
  • Electronic signature which aids identification
  • A design technique of Fast Zero Power, which offers high speed and very-low power
  • This is a true device of Zero Power that neither has any power down schemes nor turbo bits
  • More effective 0.5µ E2CMOS process
  • Also, this device is reprogrammable, making use of device programmers that are of industry standard
  • You can find this in both industrial and commercial operating ranges

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XCR22V10-10VO24C

Features of the XCR22V10-10VO24C

  • Security bit which helps in preventing any unauthorized access
  • Asynchronous reset/synchronous preset capability
  • Electronic signature which aids identification
  • Map of Function/JEDEC which works with UVCMOS, Bipolar, and EECMOS 22V10s
  • The first-ever CMOS SPLD of the industry – features both the process technologies and CMOS design
  • More effective 0.5µ E2CMOS process
  • 1000 program cycles/erase guaranteed
  • Output polarity that is programmable
  • Its dynamic current is substantially lower than other competing devices
  • Ensured 20 years of data retention
  • 24-pin TSOIC which utilizes 93% less space (in-system) in contrast to the 28-pin PLCC
  • A design technique of Fast Zero Power, which offers high speed and very-low power
  • Also, this device is reprogrammable, making use of device programmers that are of industry standard

XCR22V10-7PC28C

Features of the XCR22V10-7PC28C

  • 24-pin SOIC
  • Also, this device is reprogrammable, making use of device programmers that are of industry standard
  • The first-ever CMOS SPLD of the industry – features both the process technologies and CMOS design
  • A design technique of Fast Zero Power, which offers high speed and very-low power
  • A true device of Zero Power having no power down schemes or turbo bits
  • Security bit which helps in preventing any unauthorized access
  • Furthermore, its dynamic current is substantially lower than other competing devices
  • The pin-to-pin delay of just 7.5 ns
  • Present in industrial and commercial operating ranges
  • Electronic signature which aids identification
  • Ensured 20 years of data retention
  • More effective 0.5µ E2CMOS process
  • 1000 program cycles/erase guaranteed
  • Output polarity that is programmable

XCR22V10-10SO24C

Features of the XCR22V10-10SO24C

  • A true device of Zero Power having no power down schemes or turbo bits
  • A static current below 75 µA
  • The first-ever CMOS SPLD of the industry – features both the process technologies and CMOS design
  • The pin-to-pin delay of just 7.5 ns
  • 24-pin SOIC
  • 24-pin TSOIC which utilizes 93% less space (in-system) in contrast to the 28-pin PLCC
  • Its dynamic current is substantially lower than other competing devices
  • A design technique of Fast Zero Power, which offers high speed and very-low power
  • Map of Function/JEDEC which works with UVCMOS, Bipolar, and EECMOS 22V10s
  • Also, this device is reprogrammable, making use of device programmers that are of industry standard
  • More effective 0.5µ E2CMOS process
  • 1000 program cycles guaranteed
  • Output polarity that is programmable
  • Asynchronous reset/synchronous preset capability
  • Many packaging alternatives that feature flow-through PCB friendly pinouts
  • Ensured 20 years of data retention
  • Present in industrial and commercial operating ranges
  • Design entry, as well as verification utilizing the CAE tools, which are the standards of the industry
  • Electronic signature which aids identification
  • Security bit which helps in preventing any unauthorized access
  • Also present is the 28-pin PLCC having the JEDEC pinout, which is the standard

————————————————————————————

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————————————————————————————

XCR22LV10-15VO24I

Features of XCR22LV10-15VO24I

  • Electronic signature which aids identification
  • Map of Function/JEDEC which works with UVCMOS, Bipolar, and EECMOS 22V10s
  • Asynchronous reset/synchronous preset capability
  • More effective 0.5µ E2CMOS process
  • Its dynamic current is substantially lower than other competing devices
  • The first-ever CMOS SPLD of the industry – features both the process technologies and CMOS design
  • Ensured 20 years of data retention
  • Security bit which helps in preventing any unauthorized access
  • 1000 program cycles/erase guaranteed
  • Output polarity that is programmable
  • A design technique of Fast Zero Power, which offers high speed and very-low power

XCR22V10-10PC28C

Features of XCR22V10-10PC28C

  • A true device of Zero Power having no power down schemes or turbo bits
  • A static current below 75 µA
  • The first-ever CMOS SPLD of the industry – features both the process technologies and CMOS design
  • The pin-to-pin delay of just 7.5 ns
  • 24-pin SOIC
  • A design technique of Fast Zero Power, which offers high speed and very-low power
  • More effective 0.5µ E2CMOS process
  • 24-pin TSOIC which utilizes 93% less space (in-system) in contrast to the 28-pin PLCC
  • Map of Function/JEDEC which works with UVCMOS, Bipolar, and EECMOS 22V10s
  • Also, this device is reprogrammable, making use of device programmers that are of industry standard
  • Its dynamic current is substantially lower than other competing devices
  • 1000 program cycles guaranteed

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Functional Description of the Xilinx Universal PLD

First, the XCR22LV10 adds or executes logic functions like the expressions of sum-of-products in a fixed-OR/programmable-AND logic array. The creation of functions that are user-defined occurs by the connections’ programming of the input signals to get in the array. Output structures that are user-configurable, and come like Input/Output macro cells, increase the logic flexibility further.

Output Type

You can feed the OR array’s signal directly to the combinatorial function (output pin). Furthermore, you can also latch it in the flip-flop D-type (registered function). Furthermore, the flip-flop D-type latches data present on the clock’s rising edge, where the clear terms and global preset controls it.

 

As soon as the satisfaction of the synchronous preset term occurs, the setting of the register’s Q output will be done high during the clock input’s next rising edge. During the satisfaction of the clear term, it will become set at Q LOW. This happens without considering the state of the clock. In addition, if there is a satisfaction of the two terms simultaneously, then the preset will be overridden by the clear.

Erase/Program Cycles

In addition, the XCR22LV10 programs and erases within seconds, is 100% testable, and ensures you can conduct 1000 erase/program erase cycles.

Output Polarity

The configuration of each macrocell is possible to help in implementing active Low or active High logic. With programmable polarity, there’s surely no need to use external inverters.

Output Enable

You can either enable or disable each of the I/O macrocell’s output. After satisfying the output enable term, that has the programmed logical conditions, the next step is the propagation of the output signal into the I/O pin. Otherwise, you drive the output buffer into a state of high-impedance.

 

Furthermore, under the output enable term’s control, this I/O pin may serve as either a bidirectional I/O, dedicated output, or dedicated input. When opening all the output enable term’s connection, it will enable its output buffer automatically; therefore yielding an output that is dedicated.

 

Furthermore, if all the connections are intact, then, logically this enable term becomes FALSE always. Also, the I/O will serve as an input that is dedicated.

Register Feedback Select

After the configuration of the I/O macrocell to implement any function that is registered, then you take the feedback signal that connects to the AND array from its Q output.

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I/O Select (Bi-directional)

During the configuration of the I/O macrocell in order to execute a function that is combinatorial, say (S1=1), then its feedback signal gets released from its I/O pin. For cases like this, you can use the pin as either a dedicated input, bi-directional I/O, or a dedicated output.

Power-On Reset

In order to aid easy initialization of the system, the flip-flops will power-up while the Q output becomes low. Furthermore, the XCR22LV10’s actual output has to do with the output polarity that is programmed. The rise of the VCC has to be monotonic.

Security of the Design

Another great feature of the XCR22LV10 is that it offers a special security (EEPROM) bit, which helps in preventing any unauthorized copying or reading of designs that have been programmed in the device. Furthermore, the PLD programmer sets the security bit.

 

This occurs either at the programming cycle’s conclusion or exists as a unique and separate step, once the completion of the programming of the device. After setting the security bit, reading or verification or the programming of the XCR22LV10 becomes impossible till the whole device has been initially erased using the function – bulk-erase.

TotalCMOS: A Design Technique Useful for Fast ZeroPower

It is well-known that Xilinx is the first-ever to provide a TotalCMOS SPLD, in both design technique and process technology. Furthermore, Xilinx utilizes a lot of CMOS gates. This is useful in implementing its Sum of Products rather than the usual traditional sense approach.

 

Also, the implementation of this CMOS gate lets Xilinx offer SPLDs that are both low power and high performance, thereby breaking that paradigm that in order to possess low power, there’s a need to accept a low performance.

Conclusion

We hope we have been able to cover what the Xilinx Universal PLD is all about. However, if you still have questions bothering your mind, feel free to ask us. We are here to help you.

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