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XA2C128-7CPG132I FAQ Chips
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ICs XA2C128-7CPG132I Features
– Fastest in system programming
• Available in the following package options
– PLA architecture
– Optional bus-hold, 3-state or weak pull-up on selected I/O pins
– 100-pin VQFP with 80 user I/O
– Multi-voltage I/O operation — 1.5V to 3.3V
· Superior pinout retention
– Two separate I/O banks
– 132-ball CP (0.5 mm) BGA with 100 user I/O
– Optional Schmitt-trigger input (per pin)
· Global set/reset
– Advanced design security
· DataGATE enable (DGE) signal control
– Optimized architecture for effective logic synthesis
• Guaranteed to meet full electrical specifications over TA = –40°C to +105°C with TJ Maximum = +125°C (Q-grade)
• Optimized for 1.8V systems
– Open-drain output option for Wired-OR and LED drive
· 1.8V ISP using IEEE 1532 (JTAG) interface
– Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels
– Unsurpassed low power management
– Hot pluggable
• Advanced system features
• Industry’s best 0.18 micron CMOS CPLD
• AEC-Q100 device qualification and full PPAP support available in both I-grade and extended temperature Q-grade
– IEEE1149.1 JTAG Boundary Scan Test
· 100% product term routability across function block
– Optional configurable grounds on unused I/Os
– Pb-free only for all packages
Request XA2C128-7CPG132I FPGA Quote, Pls Send Email to Sales@hillmancurtis.com Now
Xilinx XA2C128-7CPG132I Overview
The XA2C128-7CPG132I device is
designed for both high performance and low power applications. This lends power savings to high-end communication
equipment and high speed to battery operated devices. Due
to the low power stand-by and dynamic operation, overall
system reliability is improved.
This XA2C128-7CPG132I device consists of eight Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each
Function Block. The Function Blocks consist of a 40 by 56
P-term PLA and 16 macrocells which contain numerous
configuration bits that allow for combinational or registered
modes of operation.Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds. A Schmitt-trigger
input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be
configured as direct input registers to store signals directly
from input pins.The use of the clock divide (division by 2) and DualEDGE
flip-flop gives the resultant CoolCLOCK feature.DataGATE is a method to selectively disable inputs of the
CPLD that are not of interest during certain points in time.
By mapping a signal to the DataGATE function, lower power
can be achieved due to reduction in signal switching.Another feature that eases voltage translation is I/O banking. Two I/O banks are available on the XA2C128-7CPG132I device that permit easy interfacing to
3.3V, 2.5V, 1.8V, and 1.5V devices.
The Xilinx CPLDs series XA2C128-7CPG132I is CPLD CoolRunner -II Family 3K Gates 128 Macro Cells 152MHz 0.18um (CMOS) Technology 1.8V 132-Pin CS-BGA, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
XA2C128-7CPG132I Tags integrated circuit
1. Xilinx CoolRunner-II Automotive CPLD development board
2. XA2C128 evaluation board
3. CoolRunner-II Automotive CPLD evaluation kit
4. XA2C128 reference design
5. XA2C128-7CPG132I Datasheet PDF
6. CoolRunner-II Automotive CPLD XA2C128
7. CoolRunner-II Automotive CPLD starter kit
8. Xilinx XA2C128
9. XA2C128 reference design
Xilinx XA2C128-7CPG132I TechnicalAttributes
-Operating Temperature -40℃ ~ 85℃ (TA)
-Number of Gates 3000
-Number of I/O 100
-Programmable Type In System Programmable
-Package / Case 132-TFBGA, CSPBGA
-Number of Logic Elements/Blocks 8
-Voltage Supply – Internal 1.7V ~ 1.9V
-Mounting Type Surface Mount
-Number of Macrocells 128
-Supplier Device Package 132-CSPBGA (8×8)
-Delay Time tpd(1) Max 7.0ns