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XA2C128-8VQG100Q FAQ Chips
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ICs XA2C128-8VQG100Q Features
– Unsurpassed low power management
– Optional bus-hold, 3-state or weak pull-up on selected I/O pins
– Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels
· DataGATE enable (DGE) signal control
• Available in the following package options
· 100% product term routability across function block
• Guaranteed to meet full electrical specifications over TA = –40°C to +105°C with TJ Maximum = +125°C (Q-grade)
· Superior pinout retention
– PLA architecture
• AEC-Q100 device qualification and full PPAP support available in both I-grade and extended temperature Q-grade
– IEEE1149.1 JTAG Boundary Scan Test
– Advanced design security
· Global set/reset
– Two separate I/O banks
• Advanced system features
– Fastest in system programming
– Optional configurable grounds on unused I/Os
– Hot pluggable
– Pb-free only for all packages
• Industry’s best 0.18 micron CMOS CPLD
– Optional Schmitt-trigger input (per pin)
– 100-pin VQFP with 80 user I/O
· 1.8V ISP using IEEE 1532 (JTAG) interface
– 132-ball CP (0.5 mm) BGA with 100 user I/O
– Multi-voltage I/O operation — 1.5V to 3.3V
– Open-drain output option for Wired-OR and LED drive
• Optimized for 1.8V systems
– Optimized architecture for effective logic synthesis
Request XA2C128-8VQG100Q FPGA Quote, Pls Send Email to Sales@hillmancurtis.com Now
Xilinx XA2C128-8VQG100Q Overview
The XA2C128-8VQG100Q device is
designed for both high performance and low power applications. This lends power savings to high-end communication
equipment and high speed to battery operated devices. Due
to the low power stand-by and dynamic operation, overall
system reliability is improved.
This XA2C128-8VQG100Q device consists of eight Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each
Function Block. The Function Blocks consist of a 40 by 56
P-term PLA and 16 macrocells which contain numerous
configuration bits that allow for combinational or registered
modes of operation.Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds. A Schmitt-trigger
input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be
configured as direct input registers to store signals directly
from input pins.The use of the clock divide (division by 2) and DualEDGE
flip-flop gives the resultant CoolCLOCK feature.DataGATE is a method to selectively disable inputs of the
CPLD that are not of interest during certain points in time.
By mapping a signal to the DataGATE function, lower power
can be achieved due to reduction in signal switching.Another feature that eases voltage translation is I/O banking. Two I/O banks are available on the XA2C128-8VQG100Q device that permit easy interfacing to
3.3V, 2.5V, 1.8V, and 1.5V devices.
The Xilinx CPLDs series XA2C128-8VQG100Q is CPLD CoolRunner -II Family 3K Gates 128 Macro Cells 152MHz 0.18um (CMOS) Technology 1.8V 100Pin VTQFP, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
XA2C128-8VQG100Q Tags integrated circuit
1. Xilinx XA2C128
2. CoolRunner-II Automotive CPLD XA2C128
3. CoolRunner-II Automotive CPLD starter kit
4. XA2C128 evaluation board
5. XA2C128 reference design
6. XA2C128 development board
7. Xilinx CoolRunner-II Automotive CPLD development board
8. XA2C128-8VQG100Q Datasheet PDF
9. XA2C128 evaluation board
Xilinx XA2C128-8VQG100Q TechnicalAttributes
-Number of Gates 3000
-Number of Macrocells 128
-Delay Time tpd(1) Max 7.0ns
-Mounting Type Surface Mount
-Number of Logic Elements/Blocks 8
-Supplier Device Package 100-VQFP (14×14)
-Operating Temperature -40℃ ~ 105℃ (TA)
-Number of I/O 80
-Package / Case 100-TQFP
-Voltage Supply – Internal 1.7V ~ 1.9V
-Programmable Type In System Programmable