XA95144XL-15CSG144I ApplicationField
-5G Technology
-Consumer Electronics
-Artificial Intelligence
-Internet of Things
-Medical Equipment
-Wireless Technology
-Cloud Computing
-Industrial Control
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XA95144XL-15CSG144I FAQ Chips
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ICs XA95144XL-15CSG144I Features
Technology: 0.35 μm CMOS process
Slew rate control on individual outputs for reducing EMI generation
In-system programmable enabling higher system reliability through reduced handling and reducing production programming times
Refer to XA9536XL data sheet (DS598), the XA9572XL data sheet (DS599), and the XA95144XL data sheet (DS600) for pin tables
Xilinx received ISO/TS 16949 Certification in March 2005.
Bus-hold circuitry on all user pin inputs which reduces cost associated with pull-up resistors and reduces bus loading
Optimized for high-performance 3.3V systems5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals — ideal for multi-voltage system interfacing and level shiftingTechnology: 0.35 μm CMOS process
Full IEEE Standard 1149.1 boundary-scan (JTAG) for in-system device testingFast concurrent programming
AEC-Q100 device qualification and full PPAP support available in both extended temperature Q-grade and I-grade.
Input hysteresis on all user and boundary-scan pin inputs to reduce noise on input signals
Advanced system featuresIn-system programmable enabling higher system reliability through reduced handling and reducing production programming timesSuperior pin-locking and routability with FastCONNECT™ II switch matrix allowing for multiple design iterations without board re-spinsInput hysteresis on all user and boundary-scan pin inputs to reduce noise on input signalsBus-hold circuitry on all user pin inputs which reduces cost associated with pull-up resistors and reduces bus loadingFull IEEE Standard 1149.1 boundary-scan (JTAG) for in-system device testingFast concurrent programming
System frequency up to 64.5 MHz (15.5 ns)
Refer to XC9500XL Family data sheet (DS054) for architecture description
5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals — ideal for multi-voltage system interfacing and level shifting
Superior pin-locking and routability with FastCONNECT™ II switch matrix allowing for multiple design iterations without board re-spins
Guaranteed to meet full electrical specifications over TA = -40° C to +105° C with TJ Maximum = +125° C (Q-grade)
Fast concurrent programming
Available in small footprint packages
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Xilinx XA95144XL-15CSG144I Overview
The XA9500XL 3.3V CPLD Automotive XA product family is targeted for leading-edge, high-performance automotive applications that require either automotive industrial (–40°C to +85°C ambient) or extended (–40°C to +105°C ambient) temperature reconfigurable devices.
The Xilinx CPLDs series XA95144XL-15CSG144I is CPLD XA9500XL Family 3.2K Gates 144 Macro Cells 64.5MHz 0.35um, CMOS Technology 3.3V 144Pin CSBGA, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
XA95144XL-15CSG144I Tags integrated circuit
1. XA9500XL Automotive CPLD starter kit
2. XA9500XL Automotive CPLD XA95144XL
3. Xilinx XA9500XL Automotive CPLD development board
4. XA95144XL reference design
5. Xilinx XA95144XL
6. XA95144XL-15CSG144I Datasheet PDF
7. XA95144XL development board
8. XA95144XL evaluation board
9. XA95144XL reference design
Xilinx XA95144XL-15CSG144I TechnicalAttributes
-Mounting Type Surface Mount
-Number of I/O 117
-Delay Time tpd(1) Max 15.5ns
-Programmable Type In System Programmable
-Number of Logic Elements/Blocks 8
-Number of Macrocells 144
-Voltage Supply – Internal 3V ~ 3.6V
-Supplier Device Package 144-LCSBGA (12×12)
-Number of Gates 3200
-Package / Case 144-TFBGA, CSPBGA
-Operating Temperature -40℃ ~ 85℃ (TA)