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ICs XC2C512-10FGG324C Features
– Optimized architecture for effective logic synthesis
– Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels
– PLA architecture
– Advanced design security
– IEEE1149.1 JTAG Boundary Scan Test
– RealDigital 100% CMOS product term generation
• Available in multiple package options
– Optional configurable grounds on unused I/Os
– 324-ball FG (1.0mm) BGA with 270 user I/O
– 208-pin PQFP with 173 user I/O
· Global set/reset
– Global signal options with macrocell control
– Flexible clocking modes
– Open-drain output option for Wired-OR and LED drive
· Clock divider (divide by 2,4,6,8,10,12,14,16)
– Optional Schmitt-trigger input (per pin)
– Unsurpassed low power management
· Optional DualEDGE triggered registers
· 100% product term routability across function block
• Optimized for 1.8V systems
• Advanced system features
· SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility
– Four separate I/O banks
· Multiple global clocks with phase selection per
– Optional bus-hold, 3-state or weak pullup on selected I/O pins
– Fastest in system programming
· 1.8V ISP using IEEE 1532 (JTAG) interface
– Hot Pluggable
· DataGATE enable signal control
• Industry’s best 0.18 micron CMOS CPLD
– As fast as 7.1 ns pin-to-pin delays
– Multi-voltage I/O operation — 1.5V to 3.3V
– 256-ball FT (1.0mm) BGA with 212 user I/O
· Superior pinout retention
· Multiple global output enables
– Pb-free available for all packages
– As low as 14 μA quiescent current
Request XC2C512-10FGG324C FPGA Quote, Pls Send Email to Sales@hillmancurtis.com Now
Xilinx XC2C512-10FGG324C Overview
The XC2C512-10FGG324C of CoolRunner-II 512-macrocell device is designed for
both high performance and low power applications. This
lends power savings to high-end communication equipment
and high speed to battery operated devices. Due to the low
power stand-by and dynamic operation, overall system reliability is improved
This XC2C512-10FGG324C device consists of thirty two Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each
Function Block. The Function Blocks consist of a 40 by 56
P-term PLA and 16 macrocells which contain numerous
configuration bits that allow for combinational or registered
modes of operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds.
input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be
configured as “direct input” registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as
a synchronous clock source. Macrocell registers can be
individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchronously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed
using product terms on a per-macrocell or per-Function
A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help
reduce the total power consumption of the XC2C512-10FGG324C device.
Circuitry has also been included to divide one externally
supplied global clock (GCK2) by eight different selections.
This yields divide by even and odd clock frequencies.
The Xilinx Embedded – CPLDs (Complex Programmable Logic Devices) series XC2C512-10FGG324C is CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 128MHz 0.18um (CMOS) Technology 1.8V, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
XC2C512-10FGG324C Tags integrated circuit
1. XC2C512-10FGG324C Datasheet PDF
2. Xilinx XC2C512
3. CoolRunner-II CPLD evaluation kit
4. CoolRunner-II CPLD starter kit
5. XC2C512 development board
6. XC2C512 reference design
7. XC2C512 evaluation board
8. CoolRunner-II CPLD XC2C512
9. CoolRunner-II CPLD starter kit
Xilinx XC2C512-10FGG324C TechnicalAttributes
-Delay Time tpd(1) Max 9.2ns
-Supplier Device Package 324-FBGA (23×23)
-Number of I/O 270
-Number of Macrocells 512
-Programmable Type In System Programmable
-Number of Logic Elements/Blocks 32
-Number of Gates 12000
-Operating Temperature 0℃ ~ 70℃ (TA)
-Voltage Supply – Internal 1.7V ~ 1.9V
-Package / Case 324-BBGA
-Mounting Type Surface Mount