XC2C512-10FT256I ApplicationField
-Medical Equipment
-Consumer Electronics
-Industrial Control
-5G Technology
-Wireless Technology
-Artificial Intelligence
-Cloud Computing
-Internet of Things
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ICs XC2C512-10FT256I Features
· Clock divider (divide by 2,4,6,8,10,12,14,16)
– RealDigital 100% CMOS product term generation
– Optimized architecture for effective logic synthesis
macrocell
· Superior pinout retention
– Unsurpassed low power management
– Pb-free available for all packages
· Global set/reset
– 256-ball FT (1.0mm) BGA with 212 user I/O
– Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels
– Advanced design security
– Optional bus-hold, 3-state or weak pullup on selected I/O pins
– As low as 14 μA quiescent current
· Multiple global output enables
· Multiple global clocks with phase selection per
– 208-pin PQFP with 173 user I/O
· 1.8V ISP using IEEE 1532 (JTAG) interface
• Industry’s best 0.18 micron CMOS CPLD
– Fastest in system programming
– Four separate I/O banks
– As fast as 7.1 ns pin-to-pin delays
– Optional Schmitt-trigger input (per pin)
– 324-ball FG (1.0mm) BGA with 270 user I/O
· 100% product term routability across function block
– IEEE1149.1 JTAG Boundary Scan Test
– Flexible clocking modes
– Optional configurable grounds on unused I/Os
· DataGATE enable signal control
· SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility
• Advanced system features
• Available in multiple package options
– Hot Pluggable
– PLA architecture
– Open-drain output option for Wired-OR and LED drive
– Multi-voltage I/O operation — 1.5V to 3.3V
– Global signal options with macrocell control
· Optional DualEDGE triggered registers
• Optimized for 1.8V systems
· CoolCLOCK
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Xilinx XC2C512-10FT256I Overview
Features
• Optimized for 1.8V systems
– Industry’s fastest low power CPLD
– Densities from 32 to 512 macrocells
• Industry’s best 0.18 micron CMOS CPLD
– Optimized architecture for effective logic synthesis
– Multi-voltage I/O operation — 1.5V to 3.3V
• Advanced system features
– Fastest in system programming
· 1.8V ISP using IEEE 1532 (JTAG) interface
– On-The-Fly Reconfiguration (OTF)
– IEEE1149.1 JTAG Boundary Scan Test
– Optional Schmitt trigger input (per pin)
– Multiple I/O banks on all devices
– Unsurpassed low power management
· DataGATE external signal control
– Flexible clocking modes
· Optional DualEDGE triggered registers
· Clock divider (÷ 2,4,6,8,10,12,14,16)
· CoolCLOCK
– Global signal options with macrocell control
· Multiple global clocks with phase selection per macrocell
· Multiple global output enables
· Global set/reset
– Abundant product term clocks, output enables and set/resets
– Efficient control term clocks, output enables and set/resets for each macrocell and shared across function blocks
– Advanced design security
– Open-drain output option for Wired-OR and LED drive
– Optional bus-hold, 3-state or weak pullup on select I/O pins
– Optional configurable grounds on unused I/Os
– Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels on all parts
– SSTL2_1,SSTL3_1, and HSTL_1 on 128 macrocell and denser devices
– Hot pluggable
• PLA architecture
– Superior pinout retention
– 100% product term routability across function block
• Wide package availability including fine pitch:
– Chip Scale Package (CSP) BGA, Fine Line BGA,
TQFP, PQFP, VQFP, and QFN packages
– Pb-free available for all packages
• Design entry/verification using Xilinx and industry standard CAE tools
• Free software support for all densities using Xilinx® WebPACK™ tool
• Industry leading nonvolatile 0.18 micron CMOS process
– Guaranteed 1,000 program/erase cycles
– Guaranteed 20 year data retention
Family Overview
Xilinx CoolRunner™-II CPLDs deliver the high speed and
ease of use associated with the XC9500/XL/XV CPLD family
with the extremely low power versatility of the XPLA3
family in a single CPLD. This means that the exact same
parts can be used for high-speed data communications/
computing systems and leading edge portable products,
with the added benefit of In System Programming. Low
power consumption and high-speed operation are combined
into a single family that is easy to use and cost effective.
Clocking techniques and other power saving features
extend the users’ power budget. The design features are
supported starting with Xilinx ISE® 4.1i WebPACK tool.
Additional details can be found in Further Reading,
The Xilinx Embedded – CPLDs (Complex Programmable Logic Devices) series XC2C512-10FT256I is 512 MACROCELL 1.8V ZERO POWER ISP CPLD, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
XC2C512-10FT256I Tags integrated circuit
1. XC2C512 development board
2. CoolRunner-II CPLD starter kit
3. Xilinx XC2C512
4. CoolRunner-II CPLD evaluation kit
5. XC2C512-10FT256I Datasheet PDF
6. XC2C512 reference design
7. CoolRunner-II CPLD XC2C512
8. XC2C512 evaluation board
9. CoolRunner-II CPLD evaluation kit
Xilinx XC2C512-10FT256I TechnicalAttributes
-Number of I/O 212
-Operating Temperature -40℃ ~ 85℃ (TA)
-Package / Case 256-LBGA
-Delay Time tpd(1) Max 9.2ns
-Supplier Device Package 256-FTBGA (17×17)
-Programmable Type In System Programmable
-Mounting Type Surface Mount
-Voltage Supply – Internal 1.7V ~ 1.9V
-Number of Macrocells 512
-Number of Gates 12000
-Number of Logic Elements/Blocks 32
