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XC2C512-10FTG256C FAQ Chips
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ICs XC2C512-10FTG256C Features
– Fastest in system programming
• Industry’s best 0.18 micron CMOS CPLD
– Hot Pluggable
– PLA architecture
· DataGATE enable signal control
– Flexible clocking modes
– Pb-free available for all packages
· SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility
– 324-ball FG (1.0mm) BGA with 270 user I/O
· Optional DualEDGE triggered registers
– As low as 14 μA quiescent current
– Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels
· Multiple global clocks with phase selection per
• Available in multiple package options
– Advanced design security
· Global set/reset
– Optional bus-hold, 3-state or weak pullup on selected I/O pins
– Global signal options with macrocell control
· Clock divider (divide by 2,4,6,8,10,12,14,16)
– Four separate I/O banks
· Superior pinout retention
– 208-pin PQFP with 173 user I/O
• Optimized for 1.8V systems
· Multiple global output enables
– Optional configurable grounds on unused I/Os
– Open-drain output option for Wired-OR and LED drive
– Unsurpassed low power management
– RealDigital 100% CMOS product term generation
– Multi-voltage I/O operation — 1.5V to 3.3V
– IEEE1149.1 JTAG Boundary Scan Test
– As fast as 7.1 ns pin-to-pin delays
– 256-ball FT (1.0mm) BGA with 212 user I/O
· 100% product term routability across function block
· 1.8V ISP using IEEE 1532 (JTAG) interface
• Advanced system features
– Optional Schmitt-trigger input (per pin)
– Optimized architecture for effective logic synthesis
Request XC2C512-10FTG256C FPGA Quote, Pls Send Email to Sales@hillmancurtis.com Now
Xilinx XC2C512-10FTG256C Overview
The XC2C512-10FTG256C of CoolRunner-II 512-macrocell device is designed for
both high performance and low power applications. This
lends power savings to high-end communication equipment
and high speed to battery operated devices. Due to the low
power stand-by and dynamic operation, overall system reliability is improved
This XC2C512-10FTG256C device consists of thirty two Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each
Function Block. The Function Blocks consist of a 40 by 56
P-term PLA and 16 macrocells which contain numerous
configuration bits that allow for combinational or registered
modes of operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds.
input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be
configured as “direct input” registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as
a synchronous clock source. Macrocell registers can be
individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchronously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed
using product terms on a per-macrocell or per-Function
A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help
reduce the total power consumption of the XC2C512-10FTG256C device.
Circuitry has also been included to divide one externally
supplied global clock (GCK2) by eight different selections.
This yields divide by even and odd clock frequencies.
The Xilinx Embedded – CPLDs (Complex Programmable Logic Devices) series XC2C512-10FTG256C is 512 MACROCELL 1.8V ZERO POWER ISP CPLD, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
XC2C512-10FTG256C Tags integrated circuit
1. CoolRunner-II CPLD starter kit
2. XC2C512 reference design
3. Xilinx CoolRunner-II CPLD development board
4. CoolRunner-II CPLD evaluation kit
5. XC2C512 development board
6. Xilinx XC2C512
7. XC2C512-10FTG256C Datasheet PDF
8. XC2C512 evaluation board
9. CoolRunner-II CPLD evaluation kit
Xilinx XC2C512-10FTG256C TechnicalAttributes
-Number of Logic Elements/Blocks 32
-Supplier Device Package 256-FTBGA (17×17)
-Number of I/O 212
-Package / Case 256-LBGA
-Programmable Type In System Programmable
-Delay Time tpd(1) Max 9.2ns
-Number of Macrocells 512
-Voltage Supply – Internal 1.7V ~ 1.9V
-Number of Gates 12000
-Mounting Type Surface Mount
-Operating Temperature 0℃ ~ 70℃ (TA)