XC9536XL-10VQ64C ApplicationField
-Artificial Intelligence
-Industrial Control
-Medical Equipment
-Wireless Technology
-Internet of Things
-5G Technology
-Cloud Computing
-Consumer Electronics
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XC9536XL-10VQ64C FAQ Chips
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ICs XC9536XL-10VQ64C Features
– Full IEEE Std 1149.1 boundary-scan (JTAG)
– 36 to 288 macrocells, with 800 to 6400 usable gates
– Advanced 0.35 micron feature size CMOS FastFLASH technology
– Supports hot-plugging capability
– 10,000 program/erase cycles endurance rating
– 5 ns pin-to-pin logic delays, with internal system frequency up to 208 MHz
• Excellent quality and reliability
• Pin-compatible with 5V core XC9500 family in common package footprints
– Input hysteresis on all user and boundary-scan pin inputs
– In-system programmable
– Individual output enable per output pin with local inversion
– 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals
– Pb-free available for all packages
– Superior pin-locking and routability with FastCONNECT II switch matrix
– Up to 90 product-terms per macrocell with individual product-term allocation
• Fast concurrent programming
– Extra wide 54-input Function Blocks
support on all devices
– Bus-hold circuitry on all user pin inputs
– Small footprint packages including VQFPs, TQFPs and CSPs (Chip Scale Package)
– 3.3V or 2.5V output capability
• Enhanced data security features
– Local clock inversion with three global and one product-term clocks
• Optimized for high-performance 3.3V systems
• Four pin-compatible device densities
• Advanced system features
– 20 year data retention
• Slew rate control on individual outputs
– Lower power operation
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Xilinx XC9536XL-10VQ64C Overview
The FastFLASH XC9536XL-10VQ64C is a 3.3V CPLD family
targeted for high-performance, low-voltage applications in
leading-edge communications and computing systems,
where high device reliability and low power dissipation is
important. Each XC9536XL-10VQ64C device supports in-system programming (ISP) and the full IEEE Std 1149.1 (JTAG) boundary-scan, allowing superior debug and design iteration
capability for small form-factor packages. The XC9500XL
family is designed to work closely with the Xilinx Virtex,
Spartan-XL and XC4000XL FPGA families, allowing system designers to partition logic optimally between fast interface circuitry and high-density general purpose logic. logic density of the XC9536XL-10VQ64C devices
ranges from 800 to 6400 usable gates with 36 to 288 registers, respectively. The XC9500XL family
members are fully pin-compatible, allowing easy design
migration across multiple density options in a given package
footprint. The XC9536XL-10VQ64C architectural features address the requirements of in-system programmability. Enhanced pin-locking
capability avoids costly board rework. In-system programming throughout the full commercial operating range and a
high programming endurance rating provide worry-free
reconfigurations of system field upgrades. Extended data
retention supports longer and more reliable system operating life.
Advanced system features include output slew rate control
and user-programmable ground pins to help reduce system
noise. Each user pin is compatible with 5V, 3.3V, and 2.5V
inputs, and the outputs may be configured for 3.3V or 2.5V operation. The XC9536XL-10VQ64C device exhibits symmetric full
3.3V output voltage swing to allow balanced rise and fall
times.
The Xilinx Programmable logic array series XC9536XL-10VQ64C is XC9536XL High PerformanceCPLD, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
XC9536XL-10VQ64C Tags integrated circuit
1. High-Performance CPLD evaluation kit
2. High-Performance CPLD XC9536XL
3. XC9536XL evaluation board
4. Xilinx High-Performance CPLD development board
5. High-Performance CPLD starter kit
6. XC9536XL development board
7. Xilinx XC9536XL
8. XC9536XL reference design
9. Xilinx High-Performance CPLD development board
Xilinx XC9536XL-10VQ64C TechnicalAttributes
-Operating Temperature 0℃ ~ 70℃ (TA)
-Mounting Type Surface Mount
-Number of I/O 36
-Delay Time tpd(1) Max 10.0ns
-Number of Gates 800
-Number of Macrocells 36
-Package / Case 64-TQFP
-Number of Logic Elements/Blocks 2
-Voltage Supply – Internal 3V ~ 3.6V
-Programmable Type In System Programmable (min 10K program/erase cycles)
-Supplier Device Package 64-VQFP (10×10)
