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XC9536XL-7VQG64C FAQ Chips
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ICs XC9536XL-7VQG64C Features
• Enhanced data security features
– Local clock inversion with three global and one product-term clocks
• Advanced system features
– Full IEEE Std 1149.1 boundary-scan (JTAG)
– Extra wide 54-input Function Blocks
– Lower power operation
• Pin-compatible with 5V core XC9500 family in common package footprints
– 36 to 288 macrocells, with 800 to 6400 usable gates
– Pb-free available for all packages
– Supports hot-plugging capability
support on all devices
– 5 ns pin-to-pin logic delays, with internal system frequency up to 208 MHz
• Optimized for high-performance 3.3V systems
– Superior pin-locking and routability with FastCONNECT II switch matrix
– Bus-hold circuitry on all user pin inputs
– Up to 90 product-terms per macrocell with individual product-term allocation
• Slew rate control on individual outputs
– 10,000 program/erase cycles endurance rating
– In-system programmable
– 20 year data retention
– Small footprint packages including VQFPs, TQFPs and CSPs (Chip Scale Package)
• Excellent quality and reliability
– 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals
• Fast concurrent programming
– Individual output enable per output pin with local inversion
– Advanced 0.35 micron feature size CMOS FastFLASH technology
• Four pin-compatible device densities
– Input hysteresis on all user and boundary-scan pin inputs
– 3.3V or 2.5V output capability
Request XC9536XL-7VQG64C FPGA Quote, Pls Send Email to Sales@hillmancurtis.com Now
Xilinx XC9536XL-7VQG64C Overview
The FastFLASH XC9536XL-7VQG64C is a 3.3V CPLD family
targeted for high-performance, low-voltage applications in
leading-edge communications and computing systems,
where high device reliability and low power dissipation is
important. Each XC9536XL-7VQG64C device supports in-system programming (ISP) and the full IEEE Std 1149.1 (JTAG) boundary-scan, allowing superior debug and design iteration
capability for small form-factor packages. The XC9500XL
family is designed to work closely with the Xilinx Virtex,
Spartan-XL and XC4000XL FPGA families, allowing system designers to partition logic optimally between fast interface circuitry and high-density general purpose logic. logic density of the XC9536XL-7VQG64C devices
ranges from 800 to 6400 usable gates with 36 to 288 registers, respectively. The XC9500XL family
members are fully pin-compatible, allowing easy design
migration across multiple density options in a given package
footprint. The XC9536XL-7VQG64C architectural features address the requirements of in-system programmability. Enhanced pin-locking
capability avoids costly board rework. In-system programming throughout the full commercial operating range and a
high programming endurance rating provide worry-free
reconfigurations of system field upgrades. Extended data
retention supports longer and more reliable system operating life.
Advanced system features include output slew rate control
and user-programmable ground pins to help reduce system
noise. Each user pin is compatible with 5V, 3.3V, and 2.5V
inputs, and the outputs may be configured for 3.3V or 2.5V operation. The XC9536XL-7VQG64C device exhibits symmetric full
3.3V output voltage swing to allow balanced rise and fall
The Xilinx CPLDs series XC9536XL-7VQG64C is CPLD XC9500XL Family 800 Gates 36 Macro Cells 125MHz 0.35um (CMOS) Technology 3.3V 64-Pin VTQFP , View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
XC9536XL-7VQG64C Tags integrated circuit
1. Xilinx High-Performance CPLD development board
2. XC9536XL-7VQG64C Datasheet PDF
3. Xilinx XC9536XL
4. XC9536XL development board
5. High-Performance CPLD XC9536XL
6. High-Performance CPLD evaluation kit
7. High-Performance CPLD starter kit
8. XC9536XL reference design
9. XC9536XL development board
Xilinx XC9536XL-7VQG64C TechnicalAttributes
-Mounting Type Surface Mount
-Supplier Device Package 64-VQFP (10×10)
-Number of Gates 800
-Number of I/O 36
-Number of Logic Elements/Blocks 2
-Voltage Supply – Internal 3V ~ 3.6V
-Delay Time tpd(1) Max 7.5ns
-Programmable Type In System Programmable (min 10K program/erase cycles)
-Number of Macrocells 36
-Package / Case 64-TQFP
-Operating Temperature 0℃ ~ 70℃ (TA)