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XC9572XL-10CS48I FAQ Chips
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ICs XC9572XL-10CS48I Features
– 10,000 program/erase cycles endurance rating
– Advanced 0.35 micron feature size CMOS FastFLASH technology
– 20 year data retention
– Local clock inversion with three global and one product-term clocks
– Bus-hold circuitry on all user pin inputs
• Four pin-compatible device densities
– Supports hot-plugging capability
• Fast concurrent programming
• Advanced system features
– 36 to 288 macrocells, with 800 to 6400 usable gates
• Enhanced data security features
– 3.3V or 2.5V output capability
– Pb-free available for all packages
• Optimized for high-performance 3.3V systems
– Input hysteresis on all user and boundary-scan pin inputs
– 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals
• Slew rate control on individual outputs
– Full IEEE Std 1149.1 boundary-scan (JTAG)
– Extra wide 54-input Function Blocks
– Small footprint packages including VQFPs, TQFPs and CSPs (Chip Scale Package)
– Individual output enable per output pin with local inversion
• Pin-compatible with 5V core XC9500 family in common package footprints
– Up to 90 product-terms per macrocell with individual product-term allocation
– Superior pin-locking and routability with FastCONNECT II switch matrix
– Lower power operation
– In-system programmable
• Excellent quality and reliability
support on all devices
– 5 ns pin-to-pin logic delays, with internal system frequency up to 208 MHz
Request XC9572XL-10CS48I FPGA Quote, Pls Send Email to Sales@hillmancurtis.com Now
Xilinx XC9572XL-10CS48I Overview
The FastFLASH XC9500XL family is a 3.3V CPLD family targeted for high-performance, low-voltage applications in leading-edge communications and computing systems, where high device reliability and low power dissipation is important. Each XC9572XL-10CS48I device supports in-system programming (ISP) and the full IEEE Std 1149.1 (JTAG) boundary-scan, allowing superior debug and design iteration capability for small form-factor packages. The XC9500XL family is designed to work closely with the Xilinx Virtex, Spartan-XL and XC4000XL FPGA families, allowing system designers to partition logic optimally between fast interface circuitry and high-density general purpose logic. logic density of the XC9572XL-10CS48I devices ranges from 800 to 6400 usable gates with 36 to 288 registers, respectively. The XC9500XL family members are fully pin-compatible, allowing easy design migration across multiple density options in a given package footprint. The XC9572XL-10CS48I architectural features address the requirements of in-system programmability. Enhanced pin-locking capability avoids costly board rework. In-system programming throughout the full commercial operating range and a high programming endurance rating provide worry-free reconfigurations of system field upgrades. Extended data retention supports longer and more reliable system operating life. Advanced system features include output slew rate control and user-programmable ground pins to help reduce system noise. Each user pin is compatible with 5V, 3.3V, and 2.5V inputs, and the outputs may be configured for 3.3V or 2.5V operation. The XC9572XL-10CS48I device exhibits symmetric full 3.3V output voltage swing to allow balanced rise and fall times.
The Xilinx Programmable logic array series XC9572XL-10CS48I is XC9572XL High Performance CPLD, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
XC9572XL-10CS48I Tags integrated circuit
1. Xilinx XC9572XL
2. High-Performance CPLD evaluation kit
3. XC9572XL development board
4. Xilinx High-Performance CPLD development board
5. XC9572XL reference design
6. XC9572XL-10CS48I Datasheet PDF
7. XC9572XL evaluation board
8. High-Performance CPLD XC9572XL
9. Xilinx High-Performance CPLD development board
Xilinx XC9572XL-10CS48I TechnicalAttributes
-Operating Temperature -40℃ ~ 85℃ (TA)
-Mounting Type Surface Mount
-Supplier Device Package 48-CSBGA (7×7)
-Number of Gates 1600
-Programmable Type In System Programmable (min 10K program/erase cycles)
-Voltage Supply – Internal 3V ~ 3.6V
-Package / Case 48-FBGA, CSPBGA
-Number of Logic Elements/Blocks 4
-Number of Macrocells 72
-Number of I/O 38
-Delay Time tpd(1) Max 10.0ns