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XC9572XL-10PC44C FAQ Chips
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ICs XC9572XL-10PC44C Features
• Optimized for high-performance 3.3V systems
– Advanced 0.35 micron feature size CMOS FastFLASH technology
• Slew rate control on individual outputs
– Up to 90 product-terms per macrocell with individual product-term allocation
– Supports hot-plugging capability
– Lower power operation
• Advanced system features
– 10,000 program/erase cycles endurance rating
– 5 ns pin-to-pin logic delays, with internal system frequency up to 208 MHz
– 36 to 288 macrocells, with 800 to 6400 usable gates
• Excellent quality and reliability
– Individual output enable per output pin with local inversion
• Pin-compatible with 5V core XC9500 family in common package footprints
– 3.3V or 2.5V output capability
– Input hysteresis on all user and boundary-scan pin inputs
• Four pin-compatible device densities
– Local clock inversion with three global and one product-term clocks
– 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals
support on all devices
– Small footprint packages including VQFPs, TQFPs and CSPs (Chip Scale Package)
– Full IEEE Std 1149.1 boundary-scan (JTAG)
– Superior pin-locking and routability with FastCONNECT II switch matrix
– Extra wide 54-input Function Blocks
• Fast concurrent programming
– 20 year data retention
• Enhanced data security features
– Pb-free available for all packages
– In-system programmable
– Bus-hold circuitry on all user pin inputs
Request XC9572XL-10PC44C FPGA Quote, Pls Send Email to Sales@hillmancurtis.com Now
Xilinx XC9572XL-10PC44C Overview
The FastFLASH XC9500XL family is a 3.3V CPLD family targeted for high-performance, low-voltage applications in leading-edge communications and computing systems, where high device reliability and low power dissipation is important. Each XC9572XL-10PC44C device supports in-system programming (ISP) and the full IEEE Std 1149.1 (JTAG) boundary-scan, allowing superior debug and design iteration capability for small form-factor packages. The XC9500XL family is designed to work closely with the Xilinx Virtex, Spartan-XL and XC4000XL FPGA families, allowing system designers to partition logic optimally between fast interface circuitry and high-density general purpose logic. logic density of the XC9572XL-10PC44C devices ranges from 800 to 6400 usable gates with 36 to 288 registers, respectively. The XC9500XL family members are fully pin-compatible, allowing easy design migration across multiple density options in a given package footprint. The XC9572XL-10PC44C architectural features address the requirements of in-system programmability. Enhanced pin-locking capability avoids costly board rework. In-system programming throughout the full commercial operating range and a high programming endurance rating provide worry-free reconfigurations of system field upgrades. Extended data retention supports longer and more reliable system operating life. Advanced system features include output slew rate control and user-programmable ground pins to help reduce system noise. Each user pin is compatible with 5V, 3.3V, and 2.5V inputs, and the outputs may be configured for 3.3V or 2.5V operation. The XC9572XL-10PC44C device exhibits symmetric full 3.3V output voltage swing to allow balanced rise and fall times.
The Xilinx Programmable logic array series XC9572XL-10PC44C is CPLD XC9500XL 1.6K GATES 72 M CRCLLS 111.1MHZ 0.35UM 3.3V, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
XC9572XL-10PC44C Tags integrated circuit
1. XC9572XL evaluation board
2. Xilinx XC9572XL
3. High-Performance CPLD XC9572XL
4. XC9572XL-10PC44C Datasheet PDF
5. High-Performance CPLD evaluation kit
6. Xilinx High-Performance CPLD development board
7. XC9572XL development board
8. XC9572XL reference design
9. XC9572XL-10PC44C Datasheet PDF
Xilinx XC9572XL-10PC44C TechnicalAttributes
-Voltage Supply – Internal 3V ~ 3.6V
-Number of Gates 1600
-Delay Time tpd(1) Max 10.0ns
-Mounting Type Surface Mount
-Programmable Type In System Programmable (min 10K program/erase cycles)
-Number of Logic Elements/Blocks 4
-Package / Case 44-LCC (J-Lead)
-Supplier Device Package 44-PLCC (16.59×16.59)
-Number of Macrocells 72
-Operating Temperature 0℃ ~ 70℃ (TA)
-Number of I/O 34