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XC9572XL-5VQ64C FAQ Chips
Q: How can I obtain software development tools related to the Xilinx FPGA platform?
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ICs XC9572XL-5VQ64C Features
– 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals
• Optimized for high-performance 3.3V systems
• Slew rate control on individual outputs
– 3.3V or 2.5V output capability
– Pb-free available for all packages
– Local clock inversion with three global and one product-term clocks
• Enhanced data security features
– Small footprint packages including VQFPs, TQFPs and CSPs (Chip Scale Package)
– Lower power operation
– Full IEEE Std 1149.1 boundary-scan (JTAG)
– Up to 90 product-terms per macrocell with individual product-term allocation
– In-system programmable
– 10,000 program/erase cycles endurance rating
– Input hysteresis on all user and boundary-scan pin inputs
support on all devices
• Four pin-compatible device densities
– Supports hot-plugging capability
• Pin-compatible with 5V core XC9500 family in common package footprints
– Advanced 0.35 micron feature size CMOS FastFLASH technology
– 5 ns pin-to-pin logic delays, with internal system frequency up to 208 MHz
– Bus-hold circuitry on all user pin inputs
• Excellent quality and reliability
– Individual output enable per output pin with local inversion
– 20 year data retention
• Fast concurrent programming
– 36 to 288 macrocells, with 800 to 6400 usable gates
– Extra wide 54-input Function Blocks
– Superior pin-locking and routability with FastCONNECT II switch matrix
• Advanced system features
Request XC9572XL-5VQ64C FPGA Quote, Pls Send Email to Sales@hillmancurtis.com Now
Xilinx XC9572XL-5VQ64C Overview
The FastFLASH XC9500XL family is a 3.3V CPLD family targeted for high-performance, low-voltage applications in leading-edge communications and computing systems, where high device reliability and low power dissipation is important. Each XC9572XL-5VQ64C device supports in-system programming (ISP) and the full IEEE Std 1149.1 (JTAG) boundary-scan, allowing superior debug and design iteration capability for small form-factor packages. The XC9500XL family is designed to work closely with the Xilinx Virtex, Spartan-XL and XC4000XL FPGA families, allowing system designers to partition logic optimally between fast interface circuitry and high-density general purpose logic. logic density of the XC9572XL-5VQ64C devices ranges from 800 to 6400 usable gates with 36 to 288 registers, respectively. The XC9500XL family members are fully pin-compatible, allowing easy design migration across multiple density options in a given package footprint. The XC9572XL-5VQ64C architectural features address the requirements of in-system programmability. Enhanced pin-locking capability avoids costly board rework. In-system programming throughout the full commercial operating range and a high programming endurance rating provide worry-free reconfigurations of system field upgrades. Extended data retention supports longer and more reliable system operating life. Advanced system features include output slew rate control and user-programmable ground pins to help reduce system noise. Each user pin is compatible with 5V, 3.3V, and 2.5V inputs, and the outputs may be configured for 3.3V or 2.5V operation. The XC9572XL-5VQ64C device exhibits symmetric full 3.3V output voltage swing to allow balanced rise and fall times.
The Xilinx Programmable logic array series XC9572XL-5VQ64C is 1.6K Gates 72 Macro Cells 178.6MHz 0.35um (CMOS) Technology 3.3V, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
XC9572XL-5VQ64C Tags integrated circuit
1. XC9572XL-5VQ64C Datasheet PDF
2. High-Performance CPLD XC9572XL
3. XC9572XL evaluation board
4. XC9572XL reference design
5. High-Performance CPLD starter kit
6. XC9572XL development board
7. Xilinx XC9572XL
8. High-Performance CPLD evaluation kit
9. XC9572XL reference design
Xilinx XC9572XL-5VQ64C TechnicalAttributes
-Voltage Supply – Internal 3V ~ 3.6V
-Number of Gates 1600
-Number of Macrocells 72
-Package / Case 64-TQFP
-Number of I/O 52
-Number of Logic Elements/Blocks 4
-Programmable Type In System Programmable (min 10K program/erase cycles)
-Supplier Device Package 64-VQFP (10×10)
-Operating Temperature 0℃ ~ 70℃ (TA)
-Mounting Type Surface Mount
-Delay Time tpd(1) Max 5.0ns