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XCR3128XL-10CSG144I FAQ Chips
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ICs XCR3128XL-10CSG144I Features
Security bit prevents unauthorized access
Support for complex asynchronous clocking
16 product term clocks and four local control term clocks per function block
Fast programming times
Full Boundary-Scan Test (IEEE 1149.1)
Design entry/verification using Xilinx or industry standard CAE tools
Based on industry`s first TotalCMOS PLD — both CMOS design and process technologies
Four output enable controls per function block
Advanced 0.35μ five layer metal EEPROM process
3V, In-System Programmable (ISP) using JTAG IEEE 1149.1 interface
Available in commercial grade and extended voltage (2.7V to 3.6V) industrial grade
Supports hot-plugging capability
5V tolerant I/O pins
Excellent pin retention during design changes
Foldback NAND for synthesis optimization
Typical Standby Current of 17 to 18 μA at 25°C
Universal 3-state which facilitates “bed of nails” testing
Four global clocks and one universal control term clock per device
Fast Zero Power (FZP) design technique provides ultra-low power and very high speed
Available in Chip-scale BGA, Fineline BGA, and QFP packages. Pb-free available for most package types. See Xilinx Packaging for more information.
Innovative CoolRunner XPLA3 architecture combines high speed with extreme flexibility
Request XCR3128XL-10CSG144I FPGA Quote, Pls Send Email to Sales@hillmancurtis.com Now
Xilinx XCR3128XL-10CSG144I Overview
The XCR3128XL-10CSG144I is targeted for low power systems that include portable, handheld, and power sensitive applications.，includes Fast Zero Power (FZP) design technology that combines low power and high speed. With this design technique, the XCR3128XL-10CSG144I offers true pin-to-pin speeds of 5.0 ns, while simultaneously delivering power that is less than 56 μW at standby without the need for “turbo bits” or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any other CPLD. XCR3128XL-10CSG144I devices are the only TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. The FZP design technique combines fast nonvolatile memory cells with ultra-low power SRAM shadow memory to deliver the industry’s lowest power 3.3V CPLD family.CoolRunner XPLA3 CPLDs are supported by Xilinx WebPACK software and industry standard CAE tools (Mentor, Cadence/OrCAD, Exemplar Logic, Synopsys, Viewlogic, and Synplicity), using HDL editors with ABEL, VHDL, and Verilog, and/or schematic capture design entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on multiple personal computer (PC), Sun, and HP platforms.The XCR3128XL-10CSG144I is electrically reprogrammable using industry standard device programmers.
The Xilinx CPLDs series XCR3128XL-10CSG144I is CPLD CoolRunner XPLA3 Family 3K Gates 128 Macro Cells 95MHz 0.35um (CMOS) Technology 3.3V, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
XCR3128XL-10CSG144I Tags integrated circuit
1. XCR3128XL development board
2. Macrocell CPLD starter kit
3. XCR3128XL reference design
4. Macrocell CPLD XCR3128XL
5. Macrocell CPLD evaluation kit
6. XCR3128XL evaluation board
7. Xilinx XCR3128XL
8. XCR3128XL-10CSG144I Datasheet PDF
9. Macrocell CPLD XCR3128XL
Xilinx XCR3128XL-10CSG144I TechnicalAttributes
-Number of Gates 3000
-Delay Time tpd(1) Max 9.1ns
-Number of Logic Elements/Blocks 8
-Package / Case 144-TFBGA, CSPBGA
-Supplier Device Package 144-LCSBGA (12×12)
-Programmable Type In System Programmable (min 1K program/erase cycles)
-Mounting Type Surface Mount
-Number of I/O 108
-Operating Temperature -40℃ ~ 85℃ (TA)
-Number of Macrocells 128
-Voltage Supply – Internal 2.7V ~ 3.6V