XQR17V16CC44V ApplicationField
-Medical Equipment
-Consumer Electronics
-Wireless Technology
-Internet of Things
-Industrial Control
-5G Technology
-Cloud Computing
-Artificial Intelligence
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XQR17V16CC44V FAQ Chips
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ICs XQR17V16CC44V Features
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Xilinx XQR17V16CC44V Overview
Xilinx introduces the high-density QPro™ XQR17V16
series Radiation Hardened QML configuration PROMs
which provide an easy-to-use, cost-effective method for
storing large Xilinx FPGA configuration bitstreams. The
XQR17V16CC44V is a 3.3V device with a storage capacity of
16 Mb and can operate in either a serial or byte-wide mode. for simplified block diagram of the XQR17V16
device architecture.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
When the FPGA is in Master SelectMAP mode, it generates
the configuration clock that drives the PROM and the
FPGA. After the rising CCLK edge, data is available on the
PROMs DATA (D0-D7) pins. The data will be clocked into
the FPGA on the following rising edge of the CCLK. When
the FPGA is in Slave SelectMAP mode, the PROM and the
FPGA must both be clocked by an incoming signal. A freerunning oscillator can be used to drive the CCLK. Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx ISE Foundation or
ISE WebPACK software compiles the FPGA design file into
a standard Hex format, which is then transferred to most
commercial PROM programmers.
Features
• Latch-Up Immune to LET >120 MeV/cm2/mg
• Guaranteed TID of 50 kRad(Si) per spec 1019.5
• Fabricated on Epitaxial Substrate
• 16Mbit storage capacity
• Guaranteed operation over full military temperature range: –55°C to +125°C
• One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices
• Dual configuration modes
♦ Serial configuration (up to 33 Mb/s)
♦ Parallel (up to 264 Mb/s at 33 MHz)
• Simple interface to the Xilinx QPro FPGAs
• Cascadable for storing longer or multiple bitstreams
• Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions
• Low-power CMOS floating-gate process
• 3.3V supply voltage
• Available in ceramic CK44 packages(1)
• Programming support by leading programmer manufacturers
• Design support using the ISE Foundation or ISE WebPACK software packages
• Guaranteed 20 year life data retention
Programming
The devices can be programmed on programmers supplied
by Xilinx or qualified third-party vendors. The user must
ensure that the appropriate programming algorithm and the
latest version of the programmer software are used. The
wrong choice can permanently damage the device.
The Xilinx Industrial components series XQR17V16CC44V is Configuration Memory, 2MX8, Parallel/serial, CMOS, CQCC44, CERAMIC, LCC-44, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at RAYPCB.com,
and you can also search for other FPGAs products.
XQR17V16CC44V Tags integrated circuit
1. XQR17V16 reference design
2. Xilinx QPro XQR17V16 series development board
3. XQR17V16CC44V Datasheet PDF
4. XQR17V16 development board
5. XQR17V16 evaluation board
6. QPro XQR17V16 series evaluation kit
7. QPro XQR17V16 series XQR17V16
8. QPro XQR17V16 series starter kit
9. XQR17V16 development board
Xilinx XQR17V16CC44V TechnicalAttributes
